MOS Transistor Theory
• So far, we have viewed a MOS transistor as an
ideal switch (digital operation)
– Reality: less than ideal
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Introduction
• So far, we have treated transistors as ideal
switches
• An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
• Transistor gate, source, drain all have capacitance
– I = C (∆V/∆t) -> ∆t = (C/I) ∆V
– Capacitance and current determine speed
• Also explore what a “degraded level” really means
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MOS Transistor Theory
• Study conducting channel between source and drain
• Modulated by voltage applied to the gate (voltagecontrolled device)
• nMOS transistor: majority carriers are electrons
(greater mobility), p-substrate doped (positively doped)
• pMOS transistor: majority carriers are holes (less
mobility), n-substrate (negatively doped)
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Terminal Voltages
•
Mode of operation depends on Vg, Vd, Vs
– Vgs = Vg – Vs
– Vgd = Vg – Vd
– Vds = Vd – Vs = Vgs - Vgd
•
•
•
Vg
+
Vgd
-
+
Vgs
Vs
-
Vds
+
Vd
Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds ≥ 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
– Cutoff
– Linear
– Saturation
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Gate Biasing
Gate
Source
n+
SiO2
Channel
+
-
E
p-substrate
n+
Drain
• Vgs=0: no current flows from
source to drain (insulated by
two reverse biased pn
junctions
• Vgs>0: electric field created
across substrate
VSS (Gnd)
• Electrons accumulate under gate: region changes from p-type
to n-type
• Conduction path between source and drain
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nMOS
Device
Behavior
Polysilicon gate
p-substrate
Oxide insulator
Inversion
Region
(n-type)
Depletion region
Depletion region
Vgs << Vt
Accumulation
mode
Vgs = Vt
Depletion mode
Vgs > Vt
Inversion mode
• Enhancement-mode transistor: Conducts when gate bias
Vgs > Vt
• Depletion-mode transistor: Conducts when gate bias is zero
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nMOS Cutoff
• No channel
• Ids = 0
Vgs = 0
+
-
g
s
+
-
Vgd
d
n+
n+
p-type body
b
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nMOS Linear
• Channel forms
• Current flows from d to s
Vgs > Vt
– e- from s to d
+
-
g
s
• Ids increases with Vds
• Similar to linear resistor
+
-
Vgd = Vgs
d
n+
Vds = 0
n+
p-type body
b
Vgs > Vt
+
-
g
s
+
-
d
n+
n+
Vgs > Vgd > Vt
Ids
0 < Vds < Vgs-Vt
p-type body
b
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nMOS Saturation
•
•
•
•
Channel pinches off
Ids independent of Vds
We say current saturates
Similar to current source
Vgs > Vt
+
-
g
+
-
Vgd < Vt
d Ids
s
n+
n+
Vds > Vgs-Vt
p-type body
b
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I-V Characteristics
• In linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?
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Channel Charge
• MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
• Qchannel =
polysilicon
gate
gate
Vg
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, εox = 3.9)
p-type body
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+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
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Channel Charge
• MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
• Qchannel = CV
• C=
polysilicon
gate
gate
Vg
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, εox = 3.9)
p-type body
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+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
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Channel Charge
• MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
• Qchannel = CV
• C = Cg = εoxWL/tox = CoxWL
• V=
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, εox = 3.9)
p-type body
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Cox = εox / tox
gate
Vg
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
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Channel Charge
• MOS structure looks like parallel plate capacitor while
operating in inversion
– Gate – oxide – channel
• Qchannel = CV
• C = Cg = εoxWL/tox = CoxWL
• V = Vgc – Vt = (Vgs – Vds/2) – Vt
polysilicon
gate
gate
Vg
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, εox = 3.9)
p-type body
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Cox = εox / tox
James Morizio
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
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Carrier velocity
• Charge is carried by e• Carrier velocity v proportional to lateral E-field
between source and drain
• v=
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Carrier velocity
• Charge is carried by e• Carrier velocity v proportional to lateral E-field
between source and drain
• v = µE
µ called mobility
• E=
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Carrier velocity
• Charge is carried by e• Carrier velocity v proportional to lateral E-field
between source and drain
• v = µE
µ called mobility
• E = Vds/L
• Time for carrier to cross channel:
– t=
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Carrier velocity
• Charge is carried by e• Carrier velocity v proportional to lateral E-field
between source and drain
• v = µE
µ called mobility
• E = Vds/L
• Time for carrier to cross channel:
– t=L/v
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nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
I ds =
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nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds =
t
=
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nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds =
t
W
Vds
= µCox
Vgs − Vt −
Vds
2
L
V
= β Vgs − Vt − ds Vds
2
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W
β = µCox
L
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nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current
I ds =
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nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current
V
I ds = β Vgs − Vt − dsat Vdsat
2
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nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current
Vdsat
I ds = β Vgs − Vt −
V
2 dsat
=
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β
V
(
2
gs
− Vt )
2
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nMOS I-V Summary
• Shockley 1st order transistor models
Vgs < Vt
0
I ds = β Vgs − Vt −
β
V
(
2
gs
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Vds
2
− Vt )
Vds Vds < Vdsat
2
James Morizio
Vds > Vdsat
cutoff
linear
saturation
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Current-Voltage Relations
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Current-Voltage Relations
k n: transconductance of transistor
W : width-to-length ratio
L
• As W increases, more carriers available to conduct current
• As L increases, Vds diminishes in effect (more voltage
drop). Takes longer to push carriers across the transistor,
reducing current flow
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Example
• For a 0.6 µm process
From AMI Semiconductor
tox = 100 Å
µ = 350 cm2/V*s
Vt = 0.7 V
• Plot Ids vs. Vds
– Vgs = 0, 1, 2, 3, 4, 5
– Use W/L = 4/2 λ
2.5
1.5
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Vgs = 4
1
Vgs = 3
0.5
0
W
3.9 • 8.85 ⋅ 10−14
β = µ Cox = ( 350 )
L
100 ⋅ 10−8
Vgs = 5
2
Ids (mA)
–
–
–
–
0
W
W
= 120 µ A / V 2
L
L
James Morizio
Vgs = 2
Vgs = 1
1
2
3
4
5
Vds
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pMOS I-V
• All dopings and voltages are inverted for pMOS
• Mobility µp is determined by holes
– Typically 2-3x lower than that of electrons µn
– 120 cm2/V*s in AMI 0.6 µm process
• Thus pMOS must be wider to provide same
current
– In this class, assume µn / µp = 2 to 3
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Capacitance
• Any two conductors separated by an insulator
have capacitance
• Gate to channel capacitor is very important
– Creates channel charge necessary for operation
• Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is associated
with source/drain diffusion
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Gate Capacitance
• Approximate channel as connected to source
• Cgs = εoxWL/tox = CoxWL = CpermicronW
• Cpermicron is typically about 2 fF/µm
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, εox = 3.9ε0)
p-type body
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The Gate Capacitance
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Diffusion Capacitance
• Csb, Cdb
• Undesirable, called parasitic capacitance
• Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process
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Diffusion Capacitance
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Parasitic Resistances
Polysilicon gate
G
LD
Drain
contact
VGS,eff
D
S
RS
RD
W
Drain
RS = (LS/W)R + RC
RD = (LD/W)R + RC
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RC: contact resistance
R : sheet resistance per square
of drain-source diffusion
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Body Effect
• Many MOS devices on a common substrate
– Substrate voltage of all devices are normally equal
• But several devices may be connected in series
– Increase in source-to-substrate voltage as we proceed vertically
along the chain
V12
g2
d2
g1
s2
d1
Vsb2 = 0
s1
Vsb1 = 0
V11
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• Net effect: slight increase
in threshold voltage Vt,
Vt2>Vt1
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Pass Transistors
• We have assumed source is grounded
VDD
VDD
• What if source > 0?
– e.g. pass transistor passing VDD
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Pass Transistors
• We have assumed source is grounded
• What if source > 0?
– e.g. pass transistor passing VDD
VDD
VDD
• Vg = VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
• nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
• pMOS pass transistors pull no lower than Vtp
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Pass Transistor Ckts
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V SS
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Pass Transistor Ckts
V DD
V DD
V DD
V s = V DD -V tn
V s = |V tp |
V DD
V DD
V DD -V tn V DD -V tn
V DD
V DD -V tn
V DD -V tn
V DD
V SS
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V DD
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V DD -2V tn
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Effective Resistance
• Shockley models have limited value
– Not accurate enough for modern transistors
– Too complicated for much hand analysis
• Simplification: treat transistor as resistor
– Replace Ids(Vds, Vgs) with effective resistance R
• Ids = Vds/R
– R averaged across switching of digital gate
• Too inaccurate to predict current at any given time
– But good enough to predict RC delay
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RC Delay Model
• Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width
d
g
d
k
s
kC
R/k
g
g
kC
s
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s
kC
d
k
s
kC
2R/k
g
kC
kC
d
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RC Values
• Capacitance
– C = Cg = Cs = Cd = 2 fF/µm of gate width
– Values similar across many processes
• Resistance
– R ≈ 6 KΩ in 0.6um process
– Improves with shorter channel lengths
• Unit transistors
– May refer to minimum contacted device (4/2 λ)
– Or maybe 1 µm wide device
– Doesn’t matter as long as you are consistent
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Activity
1) If the width of a transistor increases, the current will
increase
decrease
not change
2) If the length of a transistor increases, the current will
increase
decrease
not change
3) If the supply voltage of a chip increases, the maximum transistor
current will
increase
decrease
not change
4) If the width of a transistor increases, its gate capacitance will
increase
decrease
not change
5) If the length of a transistor increases, its gate capacitance will
increase
decrease
not change
6) If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase
decrease
not change
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Activity
1) If the width of a transistor increases, the current will
increase
decrease
not change
2) If the length of a transistor increases, the current will
increase
decrease
not change
3) If the supply voltage of a chip increases, the maximum transistor
current will
increase
decrease
not change
4) If the width of a transistor increases, its gate capacitance will
increase
decrease
not change
5) If the length of a transistor increases, its gate capacitance will
increase
decrease
not change
6) If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase
decrease
not change
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DC Response
• DC Response: Vout vs. Vin for a gate
• Ex: Inverter
– When Vin = 0
->
Vout = VDD
– When Vin = VDD ->
Vout = 0
– In between, Vout depends on
Vin
transistor size and current
– By KCL, must settle such that
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
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VDD
Idsp
Idsn
Vout
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Transistor Operation
• Current depends on region of transistor behavior
• For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?
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nMOS Operation
Cutoff
Vgsn <
Linear
Vgsn >
Saturated
Vgsn >
Vdsn <
Vdsn >
VDD
Vin
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Idsp
Idsn
Vout
49
nMOS Operation
Cutoff
Vgsn < Vtn
Linear
Vgsn > Vtn
Saturated
Vgsn > Vtn
Vdsn < Vgsn – Vtn V > V – V
dsn
gsn
tn
VDD
Vin
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Idsp
Idsn
Vout
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nMOS Operation
Cutoff
Vgsn < Vtn
Linear
Vgsn > Vtn
Saturated
Vgsn > Vtn
Vdsn < Vgsn – Vtn V > V – V
dsn
gsn
tn
VDD
Vgsn = Vin
Vin
Vdsn = Vout
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Idsp
Idsn
Vout
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nMOS Operation
Cutoff
Linear
Saturated
Vgsn < Vtn
Vin < Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn < Vgsn – Vtn
Vout < Vin - Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn > Vgsn – Vtn
Vout > Vin - Vtn
VDD
Vgsn = Vin
Vin
Vdsn = Vout
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Idsp
Idsn
Vout
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pMOS Operation
Cutoff
Vgsp >
Linear
Vgsp <
Saturated
Vgsp <
Vdsp >
Vdsp <
VDD
Vin
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Idsp
Idsn
Vout
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pMOS Operation
Cutoff
Vgsp > Vtp
Linear
Vgsp < Vtp
Saturated
Vgsp < Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
VDD
Vin
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Idsp
Idsn
Vout
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pMOS Operation
Cutoff
Vgsp > Vtp
Linear
Vgsp < Vtp
Saturated
Vgsp < Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
VDD
Vgsp = Vin - VDD
Vtp < 0
Vdsp = Vout - VDD
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Vin
Idsp
Idsn
Vout
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pMOS Operation
Cutoff
Linear
Saturated
Vgsp > Vtp
Vin > VDD + Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp – Vtp
Vout > Vin - Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp < Vgsp – Vtp
Vout < Vin - Vtp
VDD
Vgsp = Vin - VDD
Vtp < 0
Vdsp = Vout - VDD
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Vin
Idsp
Idsn
Vout
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I-V Characteristics
• Make pMOS wider than nMOS such that βn = βp
Vgsn5
Vgsn4
Idsn
Vgsp1
Vgsp2
-VDD
Vgsn3
-Vdsp
0
VDD
Vdsn
Vgsp3
Vgsp4
Vgsn2
Vgsn1
-Idsp
Vgsp5
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DC Transfer Curve
• Transcribe points onto Vin vs. Vout plot
VDD
A
B
Vout
C
D
0
Vtn
VDD/2
E
VDD+Vtp
Vin
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VDD
58
Operating Regions
• Revisit transistor operating regions
Region
A
B
C
D
E
nMOS
pMOS
VDD
A
B
Vout
C
D
0
Vtn
VDD/2
Vin
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E
VDD+Vtp
VDD
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Operating Regions
• Revisit transistor operating regions
Region
nMOS
pMOS
A
Cutoff
Linear
B
Saturation
Linear
C
Saturation
Saturation
D
Linear
Saturation
E
Linear
Cutoff
VDD
A
B
Vout
C
D
0
Vtn
VDD/2
Vin
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E
VDD+Vtp
VDD
60
Beta Ratio
• If βp / βn ≠ 1, switching point will move from VDD/2
• Called skewed gate
• Other gates: collapse into equivalent inverter
VDD
βp
= 10
βn
Vout
2
1
0.5
βp
= 0.1
βn
0
Vin
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VDD
61
Noise Margins
• How much noise can a gate input see before it
does not recognize the input?
Output Characteristics
Logical High
Output Range
VDD
Input Characteristics
NMH
VIH
VIL
Logical Low
Output Range
Logical High
Input Range
VOH
Indeterminate
Region
NML
VOL
Logical Low
Input Range
GND
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Logic Levels
• To maximize noise margins, select logic levels at
Vout
VDD
βp/β n > 1
Vin
0
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Vout
Vin
VDD
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Logic Levels
• To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
Vout
Unity Gain Points
Slope = -1
VDD
VOH
βp/β n > 1
Vin
VOL
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0
Vtn
VIL VIH VDD- VDD
|Vtp|
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Vout
Vin
64
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