Power Dissipation
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
Dynamic Power Dissipation
Each time the capacitor gets charged through the PMOS transistor, its voltage rises from 0 to
VDD, and a certain amount of energy is drawn from the power supply. Part of this energy is
dissipated in the PMOS device, while the remainder is stored on the load capacitor. During the
high-to-low transition, this capacitor discharged, and the stored energy is dissipated in the NMOS
transistor.
Vdd
Vin
Vout
CL
∞
Energy/transition
Power =
∞
V
DD
dvout
2
EVDD = ∫ iV DD (t )VDD dt = VDD ∫ C L
dt = CLVDD ∫ dvout = C LVDD
dt
0
0
0
Energy/transition * f = CL * Vdd2 * f
f represents the frequency of energy-consuming transitions (0 -> 1)
From equation, not a function of transistor sizes! (In reality it is)
Need to reduce CL, Vdd, and f to reduce power.
Modification for Circuits with Reduced Swing
Vdd
Vdd
Vdd -Vt
CL
E 0 → 1 = CL • V dd • ( Vdd – Vt )
Can exploit reduced swing to lower power
(e.g., reduced bit-line swing in memory)
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E N = C L • V dd2 • n (N )
EN : the energy consumed for N clock cycles
n(N): the number of 0->1 transition in N clock cycles
EN
2
n (N )
P
= lim -------- • f
=  lim -----------C •V
•
• f clk
avg N
clk
dd


N
N
N→∞
L
→∞
α0
→1
=
n(N )
lim -----------N→∞ N
P avg = α0
C • Vdd 2 • f clk
•
1
→
L
Short Circuit Currents
Vdd
Vin
Vout
CL
IV D D (mA)
0.15
0.10
0.05
0.0
1.0
2.0
3.0
Vin (V)
4.0
5.0
How to keep Short-Circuit Currents Low?
Vdd
Vout
Isc~ 0
Vin
CL
Large CL
Vdd
Isc~ Imax
Vout
Vin
CL
Small CL
Leakage
Vdd
Vout
Drain Junction
Leakage
GATE
p+
p+
N
Reverse Leakage Current
Sub-Threshold
Current
+
V
- dd
I DL = J S × A
Sub-threshold current one of most compelling issues
in low-energy circuit design!
Subthreshold Leakage Component
Current does not drop abruptly to 0 at VGS =VT. The device is partly conducting ->
subthreshold conduction or weak-inversion conduction. Current decays in an
exponential fashion for VGS< VT . The current in this region is approximated by:
The closer the threshold voltage is to
zero, the larger the subthreshold leakage
current at V GS=0V
-2
10
-4
Thus, the choice of V T presents a tradeoff between static power and
performance (Use of dual-VT).
Device designers try to reach the highest
Ion/Ioff for a device, with a sharp turn-off
characteristics.
-6
10
ID (A)
Thus, V T is not kept smaller than 0.4V.
However, with scaling of V DD, this results
in a loss of performance.
10
-8
10
-10
Exponential
-12
VT
10
10
0
0.5
1
1.5
VGS(V)
2
2.5
Performance vs. Power Trade-offs.
Leakage currents cause a rise in static power.
This is offset by dropping VDD, which is enabled by reducing VT at no cost
in performance, and results in quadratic reduction in dynamic power.
For a 0.25um CMOS process, circuit configurations obtain the same
performance with: 3V supply – 0.7V VT; and 0.45V supply – 0.1V VT.
How are those 2 cases compared in terms of dynamic and static power?
Static Power Consumption
Vdd
Istat
Vout
Vin =5V
CL
Pstat = P (In=1) .Vdd . I stat
Wasted energy …
Should be avoided in almost all cases
Principles for Power Reduction
q
q
q
Prime choice: Reduce voltage!
§ Recent years have seen an acceleration in supply voltage
reduction
§ Design at very low voltages still open question (0.6 … 0.9 V
by 2010!)
Reduce switching activity (at logic level)
Reduce physical capacitance
§ Device Sizing: for F=20
– fopt(energy)=3.53, fopt(performance)=4.47
Power-Delay-Product (PDP) is used as a metric to balance
between low delay and power.
Impact of
Technology
Scaling
Goals of Technology Scaling
q Make
things cheaper:
§ Want to sell more functions (transistors)
per chip for the same money
§ Build same products cheaper, sell the
same part for less money
§ Price of a transistor has to be reduced
q But
also want to be faster, smaller,
lower power
Technology Scaling
q
Goals of scaling the dimensions by 30%:
§ Reduce gate delay by 30% (increase operating
frequency by 43%)
§ Double transistor density
§ Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
Die size used to increase by 14% per
generation
q Technology generation spans 2-3 years
q
Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors
Year of
Introduction
1999
Technology node
[nm]
180
Supply [V]
2000
2001
2004
2008
2011
2014
130
90
60
40
30
0.6-0.9
0.5-0.6
0.3-0.6
8
9
9-10
10
3.5-2
7.1-2.5
11-3
14.9
-3.6
1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2
Wiring levels
6-7
6-7
7
Max frequency
[GHz],Local-Global
1.2
Max µP power [W]
90
106
130
160
171
177
186
Bat. power [W]
1.4
1.7
2.0
2.4
2.1
2.3
2.5
1.6-1.4 2.1-1.6
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
Technology Evolution (1999)
Technology Scaling (1)
2
Minimum Feature Size (micron)
10
1
10
0
10
10
-1
-2
10
1960
1970
1980
1990
2000
Year
Minimum Feature Size
2010
Technology Scaling (2)
Number of components per chip
Technology Scaling (3)
tp decreases by 13%/year
50% every 5 years!
Propagation Delay
Transistor Scaling
(velocity-saturated devices)
2010 Outlook
q
Performance 2X/16 months
§ 1 TIP (terra instructions/s)
§ 30 GHz clock
q
Size
§ No of transistors: 2 Billion
§ Die: 40*40 mm
q
Power
§ 10kW!!
§ Leakage: 1/3 active Power
P.Gelsinger: µProcessors for the New Millenium, ISSCC 2001
Some interesting questions
q What
will cause this model to break?
q When will it break?
q Will the model gradually slow down?
§ Power and power density
§ Leakage
§ Process Variation