Co-Synthesis Algorithms:
HW/SW Partitioning
Part of
HW/SW Codesign of Embedded
Systems Course (CE 40-226)
Winter-Spring 2001
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Topics
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Introduction
Preliminaries
Hardware/Software Partitioning
Distributed System Co-Synthesis
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Topics
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Introduction
A Classification
Examples
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Vulcan
Cosyma
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Introduction to
HW/SW Partitioning
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The first variety of co-synthesis applications
Definition
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A HW/SW partitioning algorithm implements a
specification on some sort of multiprocessor
architecture
Usually
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Multiprocessor architecture = one CPU + some
ASICs on CPU bus
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Introduction to
HW/SW Partitioning (cont’d)
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A Terminology
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Allocation
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Synthesis methods which design the multiprocessor
topology along with the PEs and SW architecture
Scheduling
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The process of assigning PE (CPU and/or ASICs) time to
processes to get executed
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Introduction to
HW/SW Partitioning (cont’d)
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In most partitioning algorithms
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Type of CPU is fixed and given
ASICs must be synthesized
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What function to implement on each ASIC?
What characteristics should the implementation have?
Are single-rate synthesis problems
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CDFG is the starting model
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HW/SW Partitioning (cont’d)
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Normal use of architectural components
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CPU performs less computationally-intensive
functions
ASICs used to accelerate core functions
Where to use?
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High-performance applications
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No CPU is fast enough for the operations
Low-cost application
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ASIC accelerators allow use of much smaller, cheaper
CPU
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A Classification
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Criterion: Optimization Strategy
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Primal Approach
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Trade-off between Performance and Cost
Performance is the primary goal
First, all functionality in ASICs. Progressively move more
to CPU to reduce cost.
Dual Approach
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Cost is the primary goal
First, all functions in the CPU. Move operations to the
ASIC to meet the performance goal.
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A Classification (cont’d)
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Classification due to optimization strategy
(cont’d)
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Example co-synthesis systems
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Vulcan (Stanford): Primal strategy
Cosyma (Braunschweig, Germany): Dual strategy
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Co-Synthesis Algorithms:
HW/SW Partitioning
HW/SW Partitioning Examples:
Vulcan
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Partitioning Examples:
Vulcan
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
Gupta, De Micheli, Stanford University
Primal approach
1. All-HW initial implementation.
2. Iteratively move functionality to CPU to reduce
cost.
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System specification language
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HardwareC
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Is compiled into a flow graph
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Partitioning Examples:
Vulcan (cont’d)
x=a; y=b;
HardwareC
nop
1
1
x=a
y=b
cond
if (c>d)
x=e;
else y=f;
c>d
c<=d
x=e
y=f
HardwareC
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Partitioning Examples:
Vulcan (cont’d)
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Flow Graph Definition
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A variation of a (single-rate) task graph
Nodes
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Represent operations
Typically low-level operations: mult, add
Edges
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Represent data dependencies
Each contains a Boolean condition under which the edge
is traversed
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Partitioning Examples:
Vulcan (cont’d)
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Flow Graph
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is executed repeatedly at some rate
can have initiation-time constraints for each node
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t(vj)+lij  t(vj)  t(vj)+uij
can have rate constraints on each node
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mi  Ri  Mi
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Partitioning Examples:
Vulcan (cont’d)
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Vulcan Co-synthesis Algorithm
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Partitioning quantum is a thread
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Algorithm divides the flow graph into threads and
allocates them
Thread boundary is determined by
1. (always) a non-deterministic delay element, such as wait
for an external variable
2. (on choice) other points of flow graph
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Target architecture
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CPU + Co-processor (multiple ASICs)
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Partitioning Examples:
Vulcan (cont’d)
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Vulcan Co-synthesis algorithm (cont’d)
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Allocation
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Primal approach
Scheduling
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is done by a scheduler on the target CPU
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is generated as part of synthesis process
schedules all threads (both HW and SW threads)
cannot be static, due to some threads non-deterministic
initiation-time
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Partitioning Examples:
Vulcan (cont’d)
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Vulcan Co-synthesis algorithm (cont’d)
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Cost estimation
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SW implementation
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Code size
 relatively straight forward
Data size
 Biggest challenge.
 Vulcan puts some effort to find bounds for each
thread
HW implementation
 ?
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Partitioning Examples:
Vulcan (cont’d)
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Vulcan Co-synthesis algorithm (cont’d)
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Performance estimation
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Both SW- and HW-implementation
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From flow-graph, and basic execution times for the
operators
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Partitioning Examples:
Vulcan (cont’d)
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Algorithm Details
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Partitioning goal
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Allocate each thread to one of two partitions
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CPU Set: FS
Co-processor set: FH
Required execution-rate must be met, and total cost
minimized
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Partitioning Examples:
Vulcan (cont’d)
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Algorithm Details (cont’d)
 Algorithm steps
1. Put all threads in FH set
2. Iteratively do
2.1. Move some operations to FS.
2.1.1. Select a group of operations to move to FS.
2.1.2. Check performance feasibility, by computing
worst-case delay through flow-graph given the new
thread times
2.1.3. Do the move, if feasible
2.2. Incrementally update the new cost-function to reflect
the new partition
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Partitioning Examples:
Vulcan (cont’d)
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Algorithm Details (cont’d)
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Vulcan cost function
f(w) = c1Sh(FH) - c2Ss(FS) + c3B - c4P + c5|m|
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c:
weight constants
S(): Size functions
B:
Bus utilization (<1)
P:
Processor utilization (<1)
m:
total number of variables to be transferred
between the CPU and the co-processor
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Partitioning Examples:
Vulcan (cont’d)
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Algorithm Details (cont’d)
 Complementary notes
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A heuristic to minimize communication
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Once a thread is moved to FS, its immediate successors
are placed in the list for evaluation in the next iteration.
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No back-track
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Once a thread is assigned to FS, it remains there
Experimental results
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considerably faster implementations than all-SW, but
much cheaper than all-HW designs are produced
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Co-Synthesis Algorithms:
HW/SW Partitioning
HW/SW Partitioning Examples:
Cosyma
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Partitioning Examples:
Cosyma
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
Rolf Ernst, et al: Technical University of
Braunschweig, Germany
Dual approach
1. All-SW initial implementation.
2. Iteratively move basic blocks to the ASIC
accelerator to meet performance objective.
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System specification language
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Cx
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Is compiled into an ESG (Extended Syntax Graph)
ESG is much like a CDFG
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Partitioning Examples:
Cosyma (cont’d)
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Cosyma Co-synthesis Algorithm
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Partitioning quantum is a Basic Block
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Target Architecture
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A Basic Blocks is a branch-free block of program
CPU + accelerator ASIC(s)
Scheduling
Allocation
Cost Estimation
Performance Estimation
Algorithm Details
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Partitioning Examples:
Cosyma (cont’d)
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Cosyma Co-synthesis Algorithm (cont’d)
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Performance Estimation
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SW implementation
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HW implementation
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Done by examining the object code for the basic block
generated by a compiler
Assumes one operator per clock cycle.
Creates a list schedule for the DFG of the basic block.
Depth of the list gives the number of clock cycles required.
Communication
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Done by data-flow analysis of the adjacent basic blocks.
In Shared-Memory
 Proportional to number of variables to be accessed
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Partitioning Examples:
Cosyma (cont’d)
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Algorithm Steps
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Change in execution-time caused by moving basic
block b from CPU to ASIC:
Dc(b) = w( tHW(b)-tSW(b) + tcom(Z) - tcom(ZUb)) x It(b)
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w:
Constant weight
t(b):
Execution time of basic block b
tcom(b): Estimated communication time between CPU and
the accelerator ASIC, given a set Z of basic blocks
implemented on the ASIC
It(b):
Total number of times that b is executed
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Partitioning Examples:
Cosyma (cont’d)
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Experimental Results
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By moving only basic-blocks to HW
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Typical speedup of only 2x
Reason:
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Cure:
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Limited intra-basic-block parallelism
Implement several control-flow optimizations to increase
parallelism in the basic block, and hence in ASIC
Examples: loop pipelining, speculative branch execution with
multiple branch prediction, operator pipelining
Result:
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Speedups: 2.7 to 9.7
CPU times: 35 to 304 seconds on a typical workstation
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What we learned today
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HW/SW Partitioning: One broad category of
co-synthesis algorithms
Criteria by which a co-synthesis algorithm is
categorized
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