Modules in
SystemC
Part of
HW/SW Codesign of Embedded
Systems Course (CE 40-226)
Winter-Spring 2001
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Today programme
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Modules in SystemC
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Module
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Advantages
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

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Building Block in Design Hierarchy
Team Work
Design Encapsulation
Design Re-use
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Module (cont’d)
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Ingredients
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Module Ports
Module Signals
Internal Data Storage
Processes
Module Constructors
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Module (cont’d)
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Module Hierarchy

Key to Implementing Complex Designs

Divide and Conquer
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Hierarchical Module
Example

MAC (Multiply-Accumulate) module
x
e
+
f
Register
a
c
d
clk
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Hierarchical MAC Module
Example (cont’d)
x
c
e
+
f
clk
SC_MODULE(mac) {
sc_in<int> a,c;
sc_in<bool> clk;
sc_out<int> d;
sc_signal<int> e,f;
reg
mult
adder
*r;
*m;
*add;
Winter-Spring 2001
Register
a
d
SC_CTOR(mac) {
r=new reg(“Register”);
m=new mult(“Mult”);
add=new adder(“Adder”);
//Named connection
//Positional
connection
r->d(f);
(*r)(f,d);
r->q(d);
(*m)(a,c,e);
m->a(a);
m->b(c);
(*add)(d,e,f);
} m->c(e);
};
add->a(d);
add->b(e);
add->c(f);
}
};
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Hierarchical MAC Module
Example (cont’d)

Write down Adder and Multiplier
modules in SystemC.
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Hierarchical Module
Example2

Register Module
q
d
DFF
DFF
DFF
DFF
clk
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Hierarchical Register Module
Example (cont’d)
#include "dff.h"
#define REG_WIDTH 10
SC_MODULE(reg) {
sc_in<bool> d[REG_WIDTH];
sc_in<bool> clk;
sc_out<bool> q[REG_WIDTH];
DFF *ff[REG_WIDTH];
SC_CTOR(reg) {
for(int i=0; i<REG_WIDTH; i++) {
ff[i] = new DFF( itoa(i,NULL,10) );
ff[i]->d(d[i]);
ff[i]->q(q[i]);
ff[i]->clk(clk);
}
}
};
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Hierarchical Register Module
Example (cont’d)

Rewrite “Register module” in positional
connection format. DFF declaration
follows:
SC_MODULE(DFF) {
sc_in<bool> d, clk;
sc_out<bool> q;
...
}
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Module (cont’d)
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Ingredients
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
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Module Ports
Module Signals
Internal Data Storage
Processes
Module Constructors
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Internal Data Storage:
Counter Module
SC_MODULE(counter) {
sc_in<bool> load;
sc_in<int> din;
sc_in<bool> clock;
sc_out<int> dout;
void counter::count_up() {
if (load)
count_val = din;
else
count_val++;
dout = count_val;
}
int count_val;
void count_up();
SC_CTOR(counter) {
SC_METHOD(count_up);
sensitive_pos << clock;
}
};
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Processes


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Implement the real function of the module
Are identified to SystemC Kernel at module
instantiation time
Are called by SystemC Kernel whenever a
change is made on their “Sensitivity List”
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Module Constructor
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
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Identify module Processes, and their
“sensitivity list” to “SystemC Kernel”
Create and initialize Internal Data Structures
of the module
Initialize Internal Data Storage
Instance name of the module is passed to the
constructor at instantiation time

Helps in reporting debug, error, and information
messages from the module
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What we learned today
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Module Concept in SystemC
Module Ingredients in SystemC
Hierarchical Design Using Modules
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Complementary notes:
Assignments
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DON’T FORGET
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Today is due date for Assignmentak 3
Take Assignment 4
Due date: Sat. Ordibehesht 1st
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Complementary notes:

Verilog Classes


Today class won’t be held
Synthesis Seminar

Sat., Ordibehesht 8th
Winter-Spring 2001
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First Quiz

Write a SystemC model for a
synchronous up-counter with
asynchronous load and clear
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