Essential Issues in Codesign:
Architectures
Part of
HW/SW Codesign of Embedded
Systems Course (CE 40-226)
Winter-Spring 2001
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Today programme
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Essential issues in codesign
 Models
 Architectures
 Languages
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Architectures
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Supplements Models by specifying how the
system will actually be implemented
Goal of each architecture is to describe
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Number of components
Type of each component
Type of each connection among above components
General classification
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Application-specific architectures: DSP
General-purpose architectures: CISC, RISC
Parallel processors: VLIW, SIMD, MIMD
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Architectures:
Controller Architecture
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Most suitably match FSM model
Consists of
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State register
Combinational blocks
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Next-state logic
Output logic
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Architectures:
Datapath Architecture
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Most suitably match DFG model
Straight-forward implementation
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Each operation in one pipeline stage
Example: FIR filter
Other enhancements
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Latches for inputs and outputs
Reducing number of functional units for one DFG
Execute multiple DFGs on a single datapath
 Need simple controllers without conditional
branches
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Architectures:
FSMD Architecture
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Combination of Controller and Datapath
architectures
Used for general-purpose processors as well
as ASICs
Each ASIC can have one or more FSMD
architectures, each with its own
characteristics
Special cases
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Controller and Datapath architectures
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CISC and RISC
architectures
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Architectures:
CISC Architecture
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Main motivation
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Reduce number of instructions in compiled
code => minimize memory accesses
Useful when
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Memory was slow and small
Programmers frequently used assembly
To support complex instructions
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Has complex datapath
Has u-programmed control
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Architectures:
CISC Architecture (cont’d)
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Clocks-per-instruction (CPI) varies for
each instruction
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Instruction pipelining is hard to implement
Relatively slow u-program memory =>
longer clock cycle
May not be well-suited for highperformance processors
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Architectures:
CISC Architecture (cont’d)
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Most frequently used instructions are
Simple instruction
Complex instructions are seldom or
never used. Because of:
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Slight semantic differences between
complex instructions and PL constructs
Difficulty in mapping PL constructs into
such complex instructions
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Architectures:
RISC Architecture
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Optimized to achieve
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Short clock cycles
Small number of CPI
Efficient pipelining of instructions
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Architectures:
RISC Architecture (cont’d)
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General organization
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Large register file + ALU
Pipeline stages:
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Fetch
Decode & Operand Fetch
Exec. ALU operation or compute addr. for data
cache
Data is stored in data-cache or register file
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Architectures:
RISC Architecture (cont’d)
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Simple design => short clock cycle,
higher performance, more complex
compiler, larger compiled-code size
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Architectures:
VLIW Architecture
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Very-Long Instruction-Word
Explicit Instruction-Level Parallelism
(ILP)
Has
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Multiple functional units in its datapath
One field for each FU in each VLIW
instruction
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Architectures:
VLIW Architecture (cont’d)
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Requires much higher bandwidth between
cpu and memory/register file
Ideally N-times faster than normal
processors. But really,
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All operands are not always in registers
All FUs are not always utilized
Technological limitations
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Efficiency and performance of register files
Requires high-pin packaging technologies
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Architectures:
Parallel Architectures
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Multiple Processing Elements (PE)
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SIMD (Single Instruction, Multiple Data)
MIMD (Multiple Instruction, Multiple Data)
SIMD or “Array Processor”
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Centralized control unit
Multiple identical Pes
Usually communication just among neighbor PEs
Most useful in computations that naturally map
into a rectangular grid
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Image processing, Weather forecasting
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Architectures:
Parallel Architectures (cont’d)
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MIMD or “Multiprocessor System”
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Each processor can communicate with each other
processor in the system
Communication mechanisms
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Shared memory
Message passing
Both of the above
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What we learned today
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Architectures are block-diagram organizational
guidelines for Implementation of systems.
Each Architecture is more suitable for a specific
Model.
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Complementary notes:
Extra classes
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“HW design using RenoirTM workshop” by A. Ganjei
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“HW Synthesis Techniques Seminar” by S. Safari
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Date-Time: Today, at 13 o’clock
Place: CE 316 (Here!)
Second session: Decide now
Postponed
Course webpage is ready. Regularly take a
look at it
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Complementary notes (cont’d)
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Subscribe to course mailing list
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Send an email from your desired email address to
majordomo@ce.sharif.edu containing:
subscribe ce226list
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Assignment 2
Project
Winter-Spring 2001
Codesign of Embedded Systems
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Happy new year!
Winter-Spring 2001
Codesign of Embedded Systems
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