Introduction to HW/SW
Co-Synthesis Algorithms
Part of
HW/SW Codesign of Embedded
Systems Course (CE 40-226)
Winter-Spring 2001
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Topics
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Introduction
Preliminaries
Hardware/Software Partitioning
Distributed System Co-Synthesis
Conclusions
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Introduction to HW/SW
Co-Synthesis Algorithms
Introduction
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Introduction
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Implementing a system? Why use CPU?
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Easier implementation
Easier (and cheaper) to change and debug
Why use hardware modules?
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Meeting other constraints
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performance, power consumption, etc
Found a CPU meeting all non-functional
constraints?
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Yes! What could be better? Use the CPU.
No! Design custom logic, or a combination of both
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Introduction (cont’d)
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Why more than one CPU or custom logic?
Why not use the fastest available CPU?
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Introduction (cont’d)
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Reason 1:
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Exponential cost per
CPU performance
Figure:
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late-1996 retail prices
of Pentium Processor
Clock speed
(MHz)
Pentium processor prices
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Introduction (cont’d)
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Exponential price/performance implies
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Paying for performance in a uni-processor is very
expensive
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Using multiple small CPUs is cheaper
Communication overhead is added, but still an economic
choice
Processors need not be CPUs. But special-function units.
Special-purpose PEs can be even cheaper than dedicated
CPU!
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Measured in system manufacturing cost, not
necessarily in design cost
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Introduction (cont’d)
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Reason 2:
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Scheduling overhead
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More than 31% overhead, under reasonable
assumptions, when executing multiple processes
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Reason: uncertainty in the times at which the processes
will need to execute
Result: we have to reserve extra CPU horsepower, which
comes at exponential cost
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Introduction (cont’d)
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Still (1997) not quite possible to declare an
authoritative taxonomy of co-synthesis
models and methods
Definition
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HW/SW co-synthesis: process of simultaneously
design the SW architecture of an application and
the HW architecture on which that SW is
executed.
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Introduction (cont’d)
SW
(app.)
Arch.
Problem
Specification
CoSynthesis
Communication
Channels
HW Engine
PE
PE
PE
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Introduction (cont’d)
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Problem specification includes
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Functionality
Non-functional requirements
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Performance goals, physical constraints, etc
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Introduction (cont’d)
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Hardware Architecture
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One or more Processing-Elements (PEs)
Software (Application) Architecture includes
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Process structure
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Each process executes sequentially
Allocation of the processes onto PEs in the HW
engine
Communication channels
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Hardware elements
Software primitives
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Introduction (cont’d)
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HW/SW Co-synthesis
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Allows trade-offs between SW architecutre and
HW on which it executes
Where is such trade-off important?
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Everyday processing applications vs. Embedded
applications
Different co-synthesis styles depending on
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The Specification
The System Components
System Elements to synthesize
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Introduction (cont’d)
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Two broad implementation styles
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HW/SW partitioning
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Target HW architecture: a CPU and multiple ASICs
Distributed System Co-synthesis
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Target HW architecture: arbitrary hardware topologies
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Introduction to HW/SW
Co-Synthesis Algorithms
Preliminaries
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Preliminaries
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Rate (execution rate)
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Maximum frequency at which a processing must
be done
Single-rate vs. Multi-rate
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Example of multi-rate system
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audio/video decoder
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Preliminaries (cont’d)
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Latency
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Required maximum time between starting and
finishing a processing task
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Preliminaries (cont’d)
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Single-rate systems
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Standard model: Control-Data Flow Graph (CDFG)
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Implies a program-counter or system-state
Software
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Control-Unit
+ Data path
Not suitable to model multi-rate tasks
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unified system state
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Preliminaries (cont’d)
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Multi-rate systems
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P1
Common model: Task
Graph
P4
P5
Task Graph
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Each Node: Process
Each Edge:
Communication
Each Set of connected
nodes: sub-task
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P2
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P3
P6
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What we learned today
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What’s co-synthesis
Various keywords used in classification of cosynthesis algorithms
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Complementary notes:
Assignments
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Take Assignment 9
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Due Date: Wednesday, Khordad 23th
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