Introduction to System-Level
Modeling in SystemC 2.0
Part of
HW/SW Codesign of Embedded
Systems Course (CE 40-226)
Winter-Spring 2001
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Topics
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A Brief Review of SystemC 1.0
Objectives of SystemC 2.0
Communication and Synchronization in
SystemC 2.0
Models of Computation within SystemC
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Introduction to System-Level
Modeling in SystemC 2.0
A Brief Review of SystemC 1.0
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Brief Review of SystemC 1.0
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A set of modeling constructs in RTL or
Behavioral abstraction level
Structural design using Modules, Ports,
and Signals
Rich set of data types including bit-true
types
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Specially: Fixed-Point data types for DSP
apps.
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Brief Review of SystemC 1.0
(cont’d)
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Concurrent Behavior is described using
Processes
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Processes can suspend and resume execution
Limited control over awakening events
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Events and sensitivity list are static (compile-time
specified)
SC_THREAD and SC_CTHREAD processes
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Can suspend and resume execution
Require their own execution stack
Memory and Context-switching time overhead
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Brief Review of SystemC 1.0
(cont’d)
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Hardware Signals are hard to model in
software
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Initialization to X
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Multiple drivers
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Used to detect reset problems
sc_logic, sc_lv data types
resolved logic signals
Not immediately change their output value
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Capability of swapping two regs on clock edge
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Brief Review of SystemC 1.0
(cont’d)
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Delayed assignment and delta cycles
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Just like VHDL and Verilog
Essential to properly model hardware
signal assignments
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Each assignment to a signal won’t be seen by
other processes until the next delta cycle
Delta cycles don’t increase user-visible time
Multiple delta cycles may occur
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Introduction to System-Level
Modeling in SystemC 2.0
Objectives of SystemC 2.0
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Objectives of SystemC 2.0
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Primary goal: Enable System-Level
Modeling
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Systems include hardware and software
Challenge:
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Wide range of design models of computation
Wide range of design abstraction levels
Wide range of design methodologies
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Objectives of SystemC 2.0
(cont’d)
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SystemC 2.0
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Introduces a small but very general purpose
modeling foundation => Core Language
Support for other models of computation,
methodologies, etc
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They are built on top of the core language, hence are
separate from it
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Even SystemC 1.0 Signals are built on top of this core in
SystemC 2.0
Other library models are provided:
 FIFO, Timers, ...
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Introduction to System-Level
Modeling in SystemC 2.0
Communication and
Synchronization in SystemC 2.0
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Communication and
Synchronization
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SystemC 1.0 Modules and Processes are still
useful in system design
But communication and synchronization
mechanisms in SystemC 1.0 (Signals) are
restrictive for system-level modeling
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Communication using queues
Synchronization (access to shared data) using
mutexes
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Communication and
Synchronization (cont’d)
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SystemC 2.0 introduces general-purpose
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Channels
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Interfaces
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A container class for communication and synchronization
They implement one or more interfaces
Specify a set of access methods to the channel
Events
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Flexible, low-level synchronization primitive
Used to construct other forms of synchronization
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Communication and
Synchronization (cont’d)
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Other comm & sync models can be built
based on the above primitives
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Examples
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HW-signals, queues (FIFO, LIFO, message queues, etc)
semaphores, memories and busses (both at RTL and
transaction-based models)
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Third Quiz
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Design a FIFO of 8 characters, along
with a producer and a consumer
process, communicating through the
FIFO
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Communication and
Synchronization (cont’d)
Interfaces
Module1
Module2
Channel
Events
Ports to Interfaces
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A Communication Modeling
Example: FIFO
Producer
Write Interface
Consumer
FIFO
Read Interface
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p
c
FIFO
FIFO Example:
Declaration of Interfaces
class write_if : public sc_interface
{
public:
virtual void write(char) = 0;
virtual void reset() = 0;
};
class read_if : public sc_interface
{
public:
virtual void read(char&) = 0;
virtual int num_available() = 0;
};
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p
c
FIFO
FIFO Example:
Declaration of FIFO channel
class fifo: public sc_channel,
public write_if,
public read_if
{
private:
enum e {max_elements=10};
char data[max_elements];
int num_elements, first;
sc_event write_event,
read_event;
bool fifo_empty() {…};
bool fifo_full() {…};
public:
fifo() : num_elements(0),
first(0);
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void write(char c) {
if (fifo_full())
wait(read_event);
data[ <you calculate> ] = c;
++num_elements;
write_event.notify();
}
void read(char &c) {
if (fifo_empty())
wait(write_event);
c = data[first];
--num_elements;
first = …;
read_event.notify();
}
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Declaration of
p
c
FIFO
FIFO channel (cont’d)
void reset() {
num_elements = first = 0;
}
int num_available() {
return num_elements;
}
}; // end of class declarations
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FIFO Example (cont’d)
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Any channel must
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be derived from sc_channel class
be derived from one (or more) classes
derived from sc_interface
provide implementations for all pure virtual
functions defined in its parent interfaces
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FIFO Example (cont’d)
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Note the following extensions beyond SystemC 1.0
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wait() call
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wait(sc_event) => dynamic sensitivity
wait(time)
wait(time_out, sc_event)
Events
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are the fundamental synchronization primitive
have no type, no value
always cause sensitive processes to be resumed
can be specified to occur:
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immediately/ one delta-step later/ some specific time later
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p
Completing the Comm.
Modeling Example
SC_MODULE(producer) {
public:
sc_port<write_if> out;
FIFO
SC_MODULE(consumer) {
public:
sc_port<read_if> in;
SC_CTOR(producer) {
SC_THREAD(main);
}
SC_CTOR(consumer) {
SC_THREAD(main);
}
void main() {
char c;
while (true) {
out.write(c);
if(…)
out.reset();
}
}
void main() {
char c;
while (true) {
in.read(c);
cout<<
};
c
in.num_available(); }
}
};
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p
c
Completing the Comm. FIFO
Modeling Example (cont’d)
SC_MODULE(top) {
public:
fifo afifo;
producer *pproducer;
consumer *pconsumer;
SC_CTOR(top) {
pproducer=new producer(“Producer”);
pproducer->out(afifo);
pconsumer=new consumer(“Consumer”);
pconsumer->in(afifo);
};
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Completing the Comm.
Modeling Example (cont’d)
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Note:
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Producer module
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sc_port<write_if> out;
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Consumer module
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sc_port<read_if> in;
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Producer can only call member functions of write_if interface
Consumer can only call member functions of read_if interface
Producer and consumer are
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unaware of how the channel works
just aware of their respective interfaces
Channel implementation is hidden from
communicating
modules
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Completing the Comm.
Modeling Example (cont’d)
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Advantages of separating communication
from functionality
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Trying different communication modules
Refine the FIFO into a software implementation
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Using queuing mechanisms of the underlying RTOS
Refine the FIFO into a hardware implementation
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Channels can contain other channels and modules
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Instantiate the hw FIFO module within FIFO channel
Implement read and write interface methods to properly
work with the hw FIFO
Refine read and write interface methods by inlining them
into producer and consumer codes
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Introduction to System-Level
Modeling in SystemC 2.0
Models of Computation within
SystemC
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Models of Computation within
SystemC
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Many different models
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The best choice is not always clear
Basic topics in a computation model
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The model of time, and event ordering constraints
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Time model: real valued, integer-valued, untimed
Event ordering: globally ordered, partially ordered
Supported methods of communication between
concurrent processes
Rules for process activation
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Models of Computation within
SystemC (cont’d)
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SystemC 2.0
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Generic model of computation
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The designer is to implement his desired model
(Virtually) all discrete-time models are supported
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Static Multi-rate Data-flow
Dynamic Multi-rate Data-flow
Kahn Process Networks
Communicating Sequential Processes
Discrete Event as used for
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RTL hardware modeling
network modeling (e.g. stochastic or “waiting room” models)
transaction-based SoC platform-modeling
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Models of Computation within
SystemC (cont’d)
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Proof of generic usage of SystemC 2.0 primitives
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Signals are realized on top of channels, interfaces, and
events
SystemC 2.0 is not suitable for continuoustime models (e.g. analog modeling)
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What we learned today
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SystemC 2.0 new features vs.
SystemC 1.0
SystemC 2.0 approach to system-level
modeling
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Separation of communication from
functionality
Providing designer with basic tools to
implement his desired model of
computation
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Complementary notes:
Assignments
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Take Assignment 7
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Due Date: Saturday, Khordad 5th
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