Design for Test of Digital Systems
TDDC33
Preliminary exam (“Dugga”)
Student
Name:
Pnr.:
Date:
Score:
Initials:
Date of last revision 25/11/2007
2007
Anders Larsson, IDA/SaS ESLAB
TDDC33 Design for Test of Digital Systems
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Introduction
This preliminary exam (“dugga”) consists of three questions. The maximum score is 8
points. The maximum allowed time to answer the questions is 15 minutes.
Admitted material: none.
Good Luck!
Question 1 (3 points)
Assume the combinational design illustrated in Figure 1. The D-notation for a 2-input OR and
a 2-input AND gate is given in Table 1 and Table 2 respectively. Determine (mark with an X)
whether the following statement is true or false:
Tests
Fault site
1
Pattern
(Stimuli, expected response)
111x, 1
Stuck-at-0
1
2
1110, 0
Stuck-at-1
2
3
1011, 1
Stuck-at-0
3
True
False
Question 2 (3 points)
Are the following statements about boundary scan true or false (mark with an X)?
1
2
3
Statement
Boundary-scan is also known as JTAG
True
False
No modification of the design is required in order to use boundaryscan
It is only possible to use one sequential boundary-scan chain on a
board
Question 3 (2 points)
Name two techniques that can be used to improve the testability of a sequential design.
TDDC33 Design for Test of Digital Systems
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INP(0)
1
OUTP(0)
2
INP(1)
INP(2)
3
INP(3)
Figure 1. Combinational design.
Table 1. D-notaion for an 2-input OR gate
_
OR
0
1
D
D
X
_
0
0
1
D
D
X
1
1
1
1
1
1
D
D
1
D
1
X
_
_
D
D
1
1
D
X
X
X
1
X
X
X
_
Table 2. D-notation for an 2-input AND gate.
_
AND
0
1
D
D
X
0
0
0
0
0
0
_
1
0
1
D
D
X
D
0
D
D
0
X
_
_
_
D
0
D
0
D
X
X
0
X
X
X
X
TDDC33 Design for Test of Digital Systems
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