Dynamic ON-resistance in
High Voltage GaN Field-Effect-Transistors
by
Donghyun Jin
B.S., Electrical Engineering, Seoul National University, 2008
S.M., Electrical Engineering and Computer Science,
Massachusetts Institute of Technology, 2010
Submitted to the Department of Electrical Engineering and Computer Science
in Partial Fulfillment of the Requirements for the Degree of
Doctor of Philosophy
at the
MASSACHUSETTS ING1TITE
OF TECHNOLOGY
Massachusetts Institute of Technology
June, 2014
©2014 Massachusetts Institute of Technology
JUN 3 0 2014
LIBRARIES
All Rights Reserved.
The author hereby grants to MIT permission to reproduce and distribute publicly paper and electronic
copies of this thesis and to grant others the right to so.
Signature redacted
Author
Department of Electrical Engineering and Computer Science
April 14, 2014
C ertified by _-_
Signature redacted
-_____-__-__-___
Jesus A. del Alamo
Professor of Electrical Engineering
A
Accepted by --------------------
------
Thesis Supervisor
Signature redacted u L'slie A. Kolodziejski
Chairman, Department Committee on Graduate Students
1
2
Dynamic ON-resistance in
High Voltage GaN Field-Effect-Transistors
by
Donghyun Jin
Submitted to the Department of Electrical Engineering and Computer Science
April 14, 2014
in Partial Fulfillment of the Requirements for the Degree of
Doctor of Philosophy
ABSTRACT
Recently, the development of energy efficient electrical power management systems has received
considerable interest due to its potential to realize significant energy savings for the world. With current
Si-based power electronics system being matured, GaN Field-Effect-Transistors have emerged as a
disruptive technology with great potential that arises from the outstanding material properties of GaN.
However, in spite of great progress in GaN device fabrication, electrical reliability and a number of
unique anomalies of GaN remain key challenges that prevent the wide deployment of this technology. In
particular, the dynamic ON-resistance (RON), in which the RON of the transistor remains high for a certain
period of time after a high-voltage OFF-ON switching event, is a critical concern. This phenomenon
greatly affects the efficiency of electrical power management circuits based on GaN power transistors.
This thesis investigates in depth this important issue.
Firstly, we have developed a new dynamic RON measurement methodology which can observe
dynamic RON transients after OFF-to-ON switching events over many decades in time. We have
experimentally demonstrated this technique on GaN-on-SiC high-voltage HEMTs (High-ElectronMobility-Transistors). The possible origin of the mechanisms responsible for dynamic RON in these
devices has been postulated. Through our new technique, the impact of high-power stress on dynamic
RON has been investigated as well. The results emphasize the importance of studying dynamic RON
characteristics over very short time scale when conducting reliability studies of GaN transistors.
Secondly, high-voltage GaN-on-Si MIS (Metal-Insulator-Semiconductor) HEMTs designed for >
600 V switching operation have been investigated. Excessive electron trapping leading to total current
collapse has been observed. We have carried out an extensive characterization of this phenomenon and
we have proposed "Zener trapping" as the responsible mechanism. In this view, electron trapping takes
place inside the AlGaN/GaN heterostructure through a tunneling process under high-electric-field. The
understanding derived here suggests that this effect can be mitigated through attention to defect control
during epitaxial growth and appropriate design of the field plate structure of the device.
Our findings in this thesis provide a path to achieve high performance GaN power transistors with
minimum dynamic RON effects.
Thesis supervisor: Jesds A. del Alamo
Title: Professor of Electrical Engineering
3
4
Acknowledgements
I sincerely appreciate my research advisor Prof. Jesds A. del Alamo for his persistent help and
great supervision throughout my PhD program. He gave me a great opportunity to work on interesting
PhD project and continuously supported me with great intuition and relevant knowledge which are crucial
to the success of my research. His high standard of research fostered the depth of this thesis. I greatly
benefited from his supervision for my PhD program as well as personal growth toward a professional
researcher. I also gratefully acknowledge Prof. David Perreault and Prof. Tomas Palacios for their
continuous encouragement and advice which were essential to accomplish my research.
I would like to thank my fantastic mentor Dr. Jungwoo Joh for his generous help and endless
advice to my research. He provided me timely answers to all kinds of different questions. I enjoyed all the
moments of our technical conversation which often took more than an hour on the phone. His invaluable
suggestion helped me in steering our research in directions of greatest relevance to industry. The regular
meeting with him plays a significant role to get essential guidance and boost up the research progress. His
proactive involvement in our research project helped me to accomplish world-class research in state-ofthe-art GaN power switching transistors.
I also would like to show my gratitude toward all the members of del Alamo's Xtreme
semiconductor group: Ling Xia, Alex Guo, Shireen Warnock, Luke Guo, Xin Zhao, Wenjie Lu, Yufei Wu,
Jianqiang Lin and Alon Vardi. Their strong enthusiasm toward research boosts me up every day and we
shared the most of joy, concern and happiness in our daily life. I also would like to thank all my
6th
floor
friends. I could spend many precious times together with you guys.
Finally, I owe a debt of gratitude to my parents and my wife, Jae Kyung for their endless love,
support and confidence throughout my entire life.
This work was sponsored by ARPE-E , SRC, DRIFT MURI and Samsung Scholarship.
5
6
Contents
Chapter 1. Introduction................................................................................................................................19
1.1.
Introduction to GaN power transistors .......................................................................
1.2.
Motivation: dynamic ON-resistance or current collapse problem...............................21
1.3.
Background .....................................................................................................................
23
1.4.
Project goal and thesis outline.....................................................................................
25
1.5.
References .......................................................................................................................
26
19
Chapter 2. Dynamic ON-resistance in high-voltage GaN-on-SiC HEMTs.............................................30
2.1.
Introduction .....................................................................................................................
30
2.2.
Proposed dynamic ON-resistance measurement technique........................................
31
2.3.
Experimental demonstration on GaN-on-SiC HEMTs...............................................
38
2.4.
Impact of epitaxial growth on dynamic ON -resistance ...............................................
45
2.5.
M echanism s responsible for dynam ic ON -resistance..................................................
50
2.6.
Conclusions .....................................................................................................................
51
2.7.
References .......................................................................................................................
52
Chapter 3. Impact of high-power stress on dynamic ON-resistance of high-voltage GaN-on-SiC HEMTs
.....................................................................................................................................................................
3.1.
Introduction .....................................................................................................................
3.2.
Experim ents.....................................................................................................................56
3.3.
D iscussion .......................................................................................................................
7
55
55
64
3.4.
Conclusions .....................................................................................................................
68
3.5.
References .......................................................................................................................
68
Chapter 4. Total current collapse in high-voltage GaN-on-Si MIS-HEMT ............................................
71
4.1.
Introduction .....................................................................................................................
71
4.2.
Experim ental set up.....................................................................................................
73
4.3.
Total current collapse under OFF-state stress ............................................................
75
4.4.
Recovery of total current collapse...............................................................................
77
4.5.
Extension and location of current blockage ................................................................
78
4.6.
Trapping and detrapping dynam ics ............................................................................
83
4.7.
Electric field sim ulation ..............................................................................................
88
4.8.
M echanism for total current collapse ..............................................................................
89
4.9.
Conclusions .....................................................................................................................
93
References ...................................................................................................................
93
4.10.
Chapter 5. Summ ary and suggestions ....................................................................................................
95
5.1.
Summ ary .........................................................................................................................
95
5.2.
Suggestions for mitigating dynamic ON-resistance phenomenon...............................97
5.3.
Suggestions for future research .....................................................................................
100
5.4.
References .....................................................................................................................
101
8
List of figures
Figure 1-1. RON transients from 200 ns up to 10,000 s of a virgin GaN transistor when switched from an
OFF-state (VGSQ= -5 V, VDsQ= 40 V) to the ON-state switching at room temperature. Blue lines are
obtained from pulsed IV system and red lines from semiconductor device analyzer, as described later in
this thesis. Also shown are the DC values of
RON
Obtained after fully detrapping the device. The results
show a 52% higher RON at 200 ns than in DC (marked as RONDC). ....
22
------------...........................................
Figure 1-2. Device model illustrating the virtual gate effect [26]..........................................................
24
Figure 2-1. ID waveform measured by pulsed IV system. The device is synchronously switched from an
OFF-state quiescent bias of VGSQ=-10 V, VDSQ=50 V to an ON-state of VGS=l V and VI)s changing from
50 mV to 1.2 V at ambient temperature of 25 'C. Through the simultaneous measurement of both
and VDS(t) transients in the linear regime, the instantaneous RON(200 ns
t
ID(t)
3 ms) is extracted as shown
on th e righ t. .................................................................................................................................................
32
Figure 2-2. RON transients from 200 ns up to 1,000 s on GaN-on-SiC high voltage HEMTs from an OFFstate (VGsQ=-5 V, VDSQ= 4 0 V) to ON-state switching at ambient temperature of 55 'C. Blue line is
obtained from pulsed IV system (Auriga AU4750) and red line from semiconductor device analyzer
(Agilent B1500A). Also shown is the DC values of
(marked as
RONDC).
RON
obtained after fully detrapping the device
This shows 66% higher RON at 200 ns than in DC.................................................33
Figure 2-3. Top: VDs and VGS waveforms of three switching events from an OFF state (VGSQ= -5 V,
VDsQ= 40 V) to the ON state. In one event, the pulsing is synchronous. In the other two, a delay of 200 ns
or 400 ns is introduced between the falling edge of VDs and the rising edge of
VGS.
Bottom: resulting
RON
transients are unaffected by the relative alignment of the VDs and VGs pulses indicating that trapping
during the transient is negligible.
In our relatively small size devices, a fast slew late of 1 V/ns is
ob tain ed .......................................................................................................................................................
9
35
Figure 2-4. Top: RON transients in OFF(VGSQ= -5 V, VDSQ= 40 V) to ON-state switching from pulsed IV
in the blue line and from SDA using different OFF-state times of 50, 75, or 100 sec. A visible mismatch
occurs with the pulsed IV data. Scaling the SDA-obtained data so as to match ARON(t)IARON(3ms) makes
all lines overlap each other as shown in dotted line. The bottom one shows identical normalized
RON
recovery rates suggesting that the RON transients are largely independent of the initial value of RON(3ms).
.....................................................................................................................................................................
Figure 2-5. Complete dynamic
RON
37
transients from 200 ns up to 10,000 s over 11 decades of time period
through our proposed technique in the section 2.2. It has been obtained on GaN-on-SiC high voltage
HEMTs from an OFF-state (VGsQ=-5 V, VDSQ= 4 0 V) to ON-state switching at ambient temperature of
2 5 C ............................................................................................................................................................
38
Figure 2-6. Top: Dynamic RON transients after OFF to ON switching events from different quiescent VDS
conditions from VDSQ=
25
V up to 125 V in 25 V increments at ambient temperature of 25 'C. Red dots
are measurements and blues lines are fitting curves through a sum of exponential terms with time
constants ranging from 10-s to 103s as shown in the bottom. The device exhibits prominent time
constants in the 10 to 1000 s range and some in the sub-ps to ms range. As VOr increases, the dynamic
RON increases too but the time constants do not change..........................................................................
40
Figure 2-7 Top: RON/RONDC transients at different ambient temperatures for VGSQ=-5 V and VDSQ= 4 0 V.
The resulting time constant spectra (bottom) clearly indicate that the dominant transients for long times
substantially speed up as the temperature increases whereas short time constants are independent of
temperature..................................................................................................................................................4
1
Figure 2-8. Arrhenius plot of time constant spectrum of Figure 2-7. The size of the symbols is
proportional to the height of the time constant peak. Dominant traps at 0.79 eV, 0.82 eV, and 0.76 eV are
identified. A set of short time constants which are independent of temperature are also observed. They are
responsible for the fast transients................................................................................................................42
10
Figure 2-9. High power to ON-state transients at different ambient temperatures and the resulting time
constant spectra (inset). The high power state bias is VGsQ=2 V and VDSQ=
7
V (the power level was 5.4
W/mm at ambient temperature of 25 0C corresponding to the red line). The transients are dominated by
temperature-independent fast time constants. No thermally activated slow-transients are observed. ........ 44
Figure 2-10. HP to ON transients from quiescent points at different VDGQ but with the same power
dissipation. Dynamic RON at 200 ns increases exponential following a hot-electron type law as shown in
th e righ t. ......................................................................................................................................................
Figure 2-11. Top: dynamic
RON
45
transients in the alternative wafer (see text) after identical OFF to ON
switching events as in Figure 2-6 at ambient temperature of 25 'C. The bottom shows the corresponding
time-constant spectra. In contrast to Figure 2-6, devices in this wafer have much weaker time constants in
the longer time periods whereas short time constants in the sub-ps to ms range dominate and do not
change as V OF increases.............................................................................................................................47
Figure 2-12. Top:
RON/RONDC
transients in devices from the alternative wafer at different ambient
temperatures for VGSQ=-5 V and VDSQ= 4 0 V. The resulting time constant spectra (bottom) show that the
dominant transients with short time constants are temperature-independent........................................48
Figure 2-13. Arrhenius plot of time constant spectrua of Figure 2-12. The size of the symbols is
proportional to the height of the time constant peak. A rich spectrum of traps with activation energies
between 0.57 eV and 1.12 eV is observed but their concentration is much lower than that in Figure 2-8.
The dominant time constants are short and do not exhibit any temperature dependence. .....................
49
Figure 2-14. Postulated mechanisms responsible for dynamic RON of GaN HEMTs observed in this work.
In the OFF state, electron trapping at the surface, in the AlGaN and at the AlGaN/A1N interface takes
place as electrons flow out the gate. In the HP state, hot electrons from the channel are trapped at
AlGaN/AIN interface states. In the ON state, electron detrapping takes place thermally for traps in the
AlGaN or at the surface and through a tunneling process for AlGaN/AlN interface traps (border traps). .51
11
Figure 3-1. The operational regions in the RF power amplifier (left) and the power-switching devices
(right) are described. The expanded RF load line (left) and the hard-switching operation (right) undergo
55
high-power state continuously which can degrade the device performance. ........................................
Figure 3-2. Time evolution of DC
RON, IDMAX
constant HP-state stress in GaN HEMTs.
RON
(normalized to their initial values) and
1IGOFI
during a
is defined by the inverse of the linear drain current
measured at VGS= 1 V and VDS= 0.5 V and IDMAX is defined at VGS= 2 V and VDS= 8 V. IGOF is the gate
leakage current measured at VGs= -5 V and VDS= 0- V. The stress conditions are VGs= 2 V and VDS= 20
V. Up to about 30 min of stress, the device characteristics show minor changes. Beyond 30 min,
prominent degradation in both RON and IDMAX and minor one in
IGOFFI
are observed.............................57
Figure 3-3. Dynamic RON transients from 200 ns up to 200 s after OFF (VGSQ= -10 V, VDsQ= 50 V) to ON
(VGs= 1 V and
VDS
1.2 V) switching event in different samples that have been subject to different HP-
state stress periods ranging from 0 to 40 min. Up to 30 min of stress, minor changes in dynamic RON are
observed. After 40 min of stress, there is a more than ten-fold increase in dynamic
RON.
Very fast
recovery in the ms range is observed in all cases...................................................................................
RON
58
Figure 3-4. Normalized dynamic RON (RON/RONDC) of Figure 3-3 at different times (200 ns, 10 ps, and 10
ms) and
RONDC/RONDC-virgin
semilog scale. Dynamic
RON_DC/RONDCvirgin
(RONDC value in the virgin device) as a function of HP-state stress time in a
RON
mostly increases in a time range from 200 ns up to a few ms.
shows small increase up to 16% in comparison to dynamic
RON
suggesting minor
perm anent (non-transient) degradation..................................................................................................
59
Figure 3-5. Time-constant spectra for RON transients of Figure 3-3. A sum of exponential terms with time
constant ranging from 100 ns to 1000 s is used to fit the measurement data. The equation used for fitting
is indicated in the inset. The fit yields the ai coefficient corresponding to each time constant Ti. These data
reveal that after 40 min of stress, there is a prominent increase of the magnitude of transients with short
time constants..............................................................................................................................................60
12
Figure 3-6. RON/RON.DC transients at different temperatures between 25 'C and 150 0 C for VGSQ= -10 V
and VDSQ= 50 V after 40 min HP stress. The inset shows the absolute value of the RON transient. As the
temperature goes up, the dominant transients are substantially accelerated. This suggests that the
transients are due to generated traps.......................................................................................................
61
Figure 3-7. Time-constant spectra for
0
RON
transients for temperatures between -55 'C and 150
C
including the transients in Figure 3-6. Arrows with different colors distinguish individual time constant
peaks at different temperatures. Most of them move towards shorter time constants as the temperature
increases indicating a thermally activated behavior..............................................................................
62
Figure 3-8. Arrhenius plot of time constant spectra from Figure 3-7. The size of the symbols is
proportional to the height of the time constant peaks and the color of them matches that of the arrows in
Figure 3-7. The dominant trap energy levels are located at 0.31, 0.45, 0.53 and 0.57 eV below the
conduction band edge most likely in the AlGaN barrier. These are the traps that are responsible for the
dramatic increase in dynamic RON that is observed in the short time scale.............................................63
Figure 3-9. Dynamic
RON
transients after OFF (VGSQ= -10 V, VDSQ= 50 V) to ON switching event for
samples subjected to HP-state stress under different conditions. The red solid line indicates a very large
increase of dynamic
RON
up to five-fold
W/mm). In comparison with the
RON DC
RON/RONDC
at 200 ns only after 3 min HP stress at VDs= 30 V (P= 9
increase after 20 min HP stress at lower VDS of 20 V and
higher P level of 12 W/mm in pink dashed line, this result suggests that HP stress at higher VDs promotes
greater dynamic RON degradation. In all cases, a very fast RON recovery down to the mrs range is observed.
.....................................................................................................................................................................
Figure 3-10. Time evolution of normalized DC
RON,
64
IDMAX and IGOFF in a constant HP-state stress in
devices made from a different epi-supplier sample (denoted as epi-supplier II). The stress conditions are
those of Figure 3-2 (VGs= 2 V, VDS= 20 V) but the stress time is extended to 2 hr. In the epi-supplier II
sample, there is no prominent permanent degradation in
1IGOFFI
RON,
IDMAX and IGOFFI. The large increase of
is fully recoverable under sufficient illumination of visible light...............................................66
13
Figure 3-11. Dynamic RON transient after an OFF (VGSQ= -10 V, VDSQ= 50 V) to ON switching event on
epi-supplier II sample before and after 2 hr HP stress at VGS= 2 V and VDs= 20 V (P~- 12 W/mm). In
contrast to the large degradation of dynamic RON in epi-supplier I device after the 40 min HP-stress
(purple dashed line), there is only a minor increase of dynamic RON observed after 2 hr HP stress in epi-
supplier I sample.........................................................................................................................................67
Figure 4-1.
Diagram of power device
characterization set-up built in the
lab. DC and AC
stress/characterization can be carried out by Agilent B1505A and Auriga pulsed IV on the Cascade Tesla
high-power probe station. Pulsed UV light source system is developed to test detrapping effect depending
on light illumination with different wavelength. Automatic computer control environment for each
instrument has been developed as well. High voltage test functionality up to 3000V is established from
the entire set-up . ..........................................................................................................................................
73
Figure 4-2. Pulsed UV light source system consisting of Xenon fiber optic light source, computer
controllable monochromator, and automated filter wheel. The brief functional description per each one is
scripted. The UV optical fiber tip drawing the output of light source system is placed closely to the
sample on the probe station, as shown on the right, so as to beam UV light directly onto the top of the
samp le ..........................................................................................................................................................
74
Figure 4-3 (a) Three field plate structures (FP1, FP2, and FP3) placed in a stairway fashion along the
gate-to-drain gap in AlGaN/GaN MIS-HEMTs. (b) The waveform of VDS and VGS in the OFF-state stepstress experiment. VDS continually steps up while VGS is biased at VT - 5 V. Every stress period is 10 s.
Between each step,
IDun which is defined at VGS= 0 V, VDS= 0.2 V is periodically monitored. IDlin is
inversely proportional to RON--.---------------------------------------------------................................................................
75
Figure 4-4. Evolution of normalized IDin in an OFF-state step-stress experiment. VGS is biased at VT- 5 V
and VDS is step-stressed by 20 V every 10 seconds up to 720 V. Total current collapse occurs for
VDSSTRES>
3 0 0
V and RON increases by
-10
orders of magnitude at the end of the experiment............76
14
Figure 4-5. Six consecutive OFF-state step-stress experiments up to 400 V on the same sample.
Detrapping procedure with UV exposer and thermal treatment (180 min at 200'C) has been applied in
between each run. Total current collapse characteristic shows complete recovery and repeatability after
78
detrapping procedures suggesting that this results from completely trapping. ......................................
Figure 4-6. Output characteristics before (blue) and after (red) 300 sec of OFF-state stress at
300 V and VGS=
VT -
VDSSTRESS=
5 V. After stress, at low VDS, nearly complete current collapse is observed.
However, as VDS increases the drain current starts flowing again. The collapsed output characteristics
resem ble a punchthrough device
...79
.................................................................................................
Figure 4-7. Evolution of the linear subthreshold characteristics
4-3. VTO is the initial threshold voltage where
D
(VDS=
0.25 V) during the stress of Figure
does not change at all under total current
-A/mm.VT
is 1
79
co llap se ........................................................................................................................................................
Figure 4-8. Evolution of source (Is), gate (IG), drain
(ID),
and substrate
(IB)
currents during the stress
periods of Figure 4-5 up to 400 V. As the OFF-state bias increases beyond 300 V, the drain-to-substrate
80
current increases. At the onset of severe trapping, all currents are negligible. ....................................
Figure 4-9. Impact of device geometry on IDun degradation under OFF-state step-stress up to
400 V and VGS=
VT -
VDSSTRESS=
5 V. The trapping characteristics do not depend on gate-to-drain gap length
1st field plate length (Lmpj),
2
(LGD),
nd field plate length (L-p2 ) and 3 rd field plate length (LFP3). .......................
81
Figure 4-10. Normalized drain-to-gate capacitance (CDG) in the OFF state as a function of VDS. The three
steps in CDG indicate the complete extension of the depletion region under each of the three field plates by
VDS=
50 V. For VDS > 50 V, electric field peaks in the channel under the edge of FP3 and where VDS is
around 200 V, excessive trapping occurs along this highly localized region and can form very short
current blockage region under the edge of FP3 as shown in the cartoon on the right.............................82
Figure 4-11. (a) Evolution of IDun in OFF-state step-stress experiment at temperatures from 25 to 200 'C.
The trapping characteristics are insensitive to temperature. (b) Evolution of drain
15
(ID),
source (Is), gate
(IG),
and substrate
(IB)
currents at different temperatures. The terminal currents are not the main source of
electron trapping..........................................................................................................................................84
Figure 4-12. (a) Evolution of normalized IDun as a function of time in a device under constant stress bias
from VDS-STRESS=140 to 180 V at room temperature. A characteristic trapping time (r) is defined at the 50%
degradation point of IDlin- (b) Zener dependence of T: T vs. 1/EPEAK in a semi-log scale.
EPEAK
is the peak
value of electric field inside AlGaN layer under FP3 estimated from field simulations in the same OFFstate bias conditions (Figure 4-13). The straight line that is obtained strongly suggests a Zener tunneling
process. A trap energy level of around 1 eV above valence band edge is estimated. ............................
Figure 4-13. Normalized IDun recovery transients in the dark after 600 sec OFF-state stress at
200 V and VGS= VT
-
85
VDSSTRESS=
5 V at different temperatures. IDlinDC is the virgin DC value of IDin- As T increases,
the recovery speeds up. An activation energy of around 0.63 eV is extracted........................................87
Figure 4-14. UV-induced recovery of a device collapsed after 300 V OFF-state stress for 3 min for
different energies of UV light at room temperature. Enhanced recovery is observed for light energies
above 2 .8 eV ................................................................................................................................................
87
Figure 4-15. (a) Evolution of electric field at the top surface of AlGaN barrier from gate to drain obtained
from TCAD simulations (Silvaco). Beyond VDs=200 V, the peak electric field appears under the edge of
the outermost field plate and increases with VDS. (b) Magnitude of EPEAK under third field-plate edge vs.
VDS is described. At VDs= 200 V,
EPEAK
is around 3.4 MV/cm and it increases up to 6.4 MV/cm at 1,000
V ..................................................................................................................................................................
88
Figure 4-16. Proposed Zener trapping mechanism responsible for the observed total current collapse.
Direct electron tunneling from the valence band into defect states can be triggered under intense electricfield inside the AlGaN barrier layer or at the top of the GaN channel...................................................90
Figure 4-17. Energy band diagram along surface from gate to drain with device biased in the linear
regime after a total current collapse event. OFF-state trapping results in a sharp energy barrier directly
below the edge of the outermost field plate that blocks current. In the linear regime, thermal detrapping
16
can take place as indicated with an activation energy substantially lower than the ionization energy of the
trap ...............................................................................................................................................................
90
Figure 4-18. Energy location of traps responsible for Zener trapping. From Zener trapping calculations,
ET - Ev = 1.0 eV is extracted and from UV detrapping experiments, Eh, = 2.8 eV is estimated...........91
Figure 4-19. Evolution of IDun under VDS=O V condition as VGS steps from -12 V to -48 V with 1 V/step
every 30 sec at room temperature. Sharp current collapse is observed as well. In this case, the channel
blockage occurs under the source end of the gate. Thermal acceleration behavior in this source-side
recovery is clearly observed with an activation energy of 0.50 eV, as shown on the right....................92
17
18
Chapter 1. Introduction
1.1.
Introduction to GaN power transistors
In our contemporary society, the standard of living has substantially improved but this
indispensably requires continuous increase of energy consumption all over the world.
However,
additional constructions of conventional power plant for the increasing energy demand confront negative
social pressure due to their externality to global warming effect. As a result, a tremendous interest has
been given to the development of energy efficient electrical power management systems along with high
expectations for significant energy saving on a world-wide scale.
The current power management system which controls or transforms electrical energy into
different power range with diverse power load such as industrial infrastructures, consumer appliances,
automotive applications, and electricity grid system has been developed through Si-based power transistor
technology in the last 60 years. In the 1950s, Si bipolar power transistors and thyristors were first
invented and in 1980s, insulated gate devices were introduced [1]. Until now, various innovative technical
improvements have been introduced through Si-based power transistor technology but nowadays their
progress has slowed down as it becomes a matured technology. In the last few years, a great deal of
attention has been given to new power transistor technologies based on new material systems. Recently
19
Gallium Nitride (GaN) power transistors have emerged as a disruptive technology with great potential
that arises from the outstanding material properties of GaN [2][3].
The wide band gap (3.4 eV) of GaN, compared to 1.12 eV of Si which dominates commercialized
power semiconductors technology today, provides several benefits in future power electronic applications.
Firstly, GaN can have a very high critical electric field, about ten times higher than Si [4], which enables
achieving a much higher breakdown voltage in GaN power-switching transistors [5]. Secondly, GaN can
have smaller intrinsic carrier densities than Si at the same temperature which provides proper electronic
functionality at ambient temperatures higher than 150 'C without external cooling. This is impossible in
Si technology due to substantial increase of leakage currents [6]. This also guarantees a much higher
thermal limit to power device operation. Moreover, GaN is a compound semiconductor including
elements from column three in the periodic table and nitrogen. It is relatively easy to form
heterostructures such as AlGaN/GaN which is the most famous one. This can induce a very high sheet
electron density in the GaN channel layer of more than 1013 cm-2 through spontaneous and piezoelectric
polarization charges without any external doping [7]. In addition, high electron saturation velocity
(2.5x 107 cm/s) with high electron mobility (> 1000 cm 2 /Vs) in the AlGaN/GaN heterostructure is
attainable and this provides very high frequency of operation as well [8]. The combination of these
superior properties promise better than three orders of magnitude improvement
in the
ON-
resistance/breakdown-voltage trade-off over conventional Si power switching devices [1].
As a result of these outstanding technical attributes, GaN transistors exhibit a significant
advantage in terms of size when compared to advanced Si power transistors. In addition, GaN
heterostructures can be grown onto wide area Si wafers [9] which enables the fabrication of GaN power
transistors in Si fabrication facilities. This mitigates the need for large investment in the creation of new
processing infrastructure. The combination of smaller device footprint and GaN-on-Si epi-growth
technology might make this technology cost competitive with Si [9].
20
As a result of the outstanding material properties and expected cost benefits of GaN power
transistor technology, intense research efforts are under way around the world. The great progress in
device performance has been achieved through diverse approaches using novel device fabrication
technologies [10]-[13] and demonstrated greater performance over Si power transistor technology.
However, in spite of recent progress in GaN device fabrication technology, a comparative study of
reliability is also required but there is not enough understanding today to carry out this critical inquiry.
Especially, electrical reliability as well as some unique anomalies of GaN still remain key challenges that
prevent the wide deployment of this technology. There are very few studies about the dominant failure
mechanisms of GaN power transistors. Significant improvement in reliability is frequently emphasized as
a final key hurdle to overcome for commercialization of this technology to become a reality[14][15].
1.2. Motivation: dynamic ON-resistance or current collapse problem
From the wide investigation in the past about the degradation mechanisms of RF power GaN
High-Electron-Mobility Transistors (HEMTs) [13],[14],[18],19], similar phenomena are considered to be
relevant in GaN power transistors as well. Among several degradation mechanisms and operational
anomalies suggested from the studies on those devices, a particular concern is the so-called dynamic ONresistance (RON) or current collapse problem [20]. Strictly speaking, this is not a reliability problem but in
order for GaN power switching-devices to outperform current Si power transistor technology this
significant anomaly needs to be resolved.
21
OFF(-5 V, 40 V) to ON
5.5
Semiconductor
Device Analyzer
Pulsed-IV
5E
E
c 4.5cI
0
4-
-10
-
11010
mm
5RONc= 3.5 Q
310710
------- ---- 10 10 102 103 10
Time [sec]
Figure 1-1. RON transients from 200 ns up to 10,000 s of a virgin GaN transistor when
switched from an OFF-state (VGSQ= -5 V, VDsQ= 40 V) to the ON-state switching at room
temperature. Blue lines are obtained from pulsed IV system and red lines from semiconductor
device analyzer, as described later in this thesis. Also shown are the DC values of RON obtained
after fully detrapping the device. The results show a 52% higher RON at 200 ns than in DC (marked
as RONDC).
Dynamic
RON
RON
or current collapse refers to a condition in which after an OFF-ON switching event,
of the transistor remains high for a certain period of time. The observation of temporary high values
of RON as a result of prominent electron trapping that occurs during the off state has been widely reported
[21]. Our recent studies have shown that dynamic
short-time scale
RON
RON
in high-voltage GaN FETs can be very severe with
values that are several times higher than RONDC which is the initial DC value of RON
[12]. The high dynamic
RON
values can take many hours to fully dissipate at room temperature, as shown
in Figure 1-1. The problem also worsens as the OFF-state voltage increases [22]. Dynamic
RON
is also
activated by hot-electron trapping under high-power conditions that might appear during hard switching
22
[23], [24]. Understanding and solving this problem will require identifying the sources of the traps that
are responsible and eliminating them.
Our goal is to achieve fundamental understanding on this problem by developing an appropriate
measurement methodology and carrying out systematic characterization of devices with various designs.
In addition, we wish to explore any degradation from the impact of various electrical stresses which can
be driven by power device operation such as high electric field stress from high blocking voltage in the
OFF-state condition or high-power stress during hard switching condition. The impact from special
device features such as multiple field plate technology on dynamic RON under electrical stress will also be
explored and the dominant mechanisms will be clarified.
1.3. Background
In this section, previous studies about this dynamic
RON
or current collapse phenomenon are
briefly introduced. An increase of RON or a collapse of drain current that depends on the operational
device history is related to the change density in the inversion layer of the AlGaN/GaN heterostructure.
The high density of 2 dimensional electron-gas (2DEG) attainable in this heterostructure not only results
from spontaneous and piezoelectric polarization effects [7] but also from the existence of a positive sheet
of charge at the top AlGaN surface which mostly arises from ionized donor states at the surface [25].
Initial studies about current collapse observed in AlGaN/GaN HEMTs claim that in the high voltage bias
condition, the accumulation of negative charge mostly through the injecting electrons from gate electrode
into the top AlGaN surface layer induces a reverse biased virtual gate effect [26]. As shown in Figure 1-2,
in the reverse bias condition between gate and drain electrodes, incoming electrons are captured by the
surface states and neutralize the positive donor states. This results in an extension of the depletion region.
In the following ON-state condition, they are usually released with relatively long time constants on the
23
order of seconds [20] and the 2DEG density along the neutralized surface region is reduced significantly
causing the dynamic RON or current collapse during high frequency operation of these devices.
Virtual Gate
++Drain
- - - - - ---- ----- ---AIGaN
VVVG
V
G aN
VG
Source
Extended depletion region
Figure 1-2. Device model illustrating the virtual gate effect [26]
In order to mitigate this virtual gate effect, surface passivation technology has been utilized [27]
using mostly SiN passivation layer [28]-[30]. There are reports of surface passivation strongly mitigating
current collapse by reducing the surface electric field and preventing the electron injection from the gate
electrode into the adjacent surface states [31]. Nowadays, surface passivation is regarded as an essential
technology which mostly determines trapping related current collapse phenomenon as well as some
device reliability issues.
Another mechanism responsible for current collapse is channel hot electron trapping under high
drain voltage operation in the ON-state [24]. In the high voltage and ON-state operating condition,
electrons flowing in the channel can obtain very high kinetic energy which enables them to overflow the
energy barrier between the AlGaN barrier and GaN channel layer and get trapped at surface states or traps
inside the barrier layer [32]. This can also cause a virtual gate effect and perhaps also permanent
degradation by trap formation resulting in current collapse [33].
24
Recently, crystallographic defect formation through the inverse piezoelectric effect has been
proposed as a new degradation mechanisms and can induce the current collapse effect as well [34]. Under
high electric field condition, the AlGaN/GaN heterostructure can get additional mechanical stress through
the inverse piezoelectric effect. If the induced total elastic energy density exceeds a critical value,
crystallographic defects such as pits and cracks can be formed. These defects can become trapping sites
for electrons and all relevant trapping effects discussed above can become magnified.
1.4.
Project goal and thesis outline
Previous studies about dynamic
RON
or current collapse have been mostly limited to simple
characterization and they fail to contribute detailed understanding. Systematic studies on this problem
have not been reported and consensus about the detailed physical origin is still lacking. In addition,
systematic studies have yet to be performed in GaN power-switching devices. In our thesis, we target an
initial rigorous investigation of this important issue. We will carry out extensive experiments under a
variety of stress conditions in devices with various geometries. There can be significant degradation of the
dynamic characteristics of GaN FETs as a result of prolonged electrical stress. The importance of
electrical reliability studies on transient characteristics, and not just DC characteristics, is emphasized.
The effectiveness of multi-field plate design in the industrially prototyped power switching device
structures studied here is investigated in detail. Lastly, theoretical degradation mechanism models are
presented.
This thesis is organized as follows. In chapter 2, we propose a new dynamic RON measurement
methodology which can observe RON transients after OFF-to-ON switching event over many decades of
time. Experimental demonstration of this technique on GaN-on-SiC high-voltage HEMTs is presented.
Impact of epitaxial growth on dynamic RON is also discussed in. Finally, relevant mechanisms responsible
for the dynamic RON observed in GaN-on-SiC HEMTs are proposed.
25
In chapter 3, by using the newly proposed technique introduced in chapter 2, the impact of highpower stress on dynamic RON characteristics of high-voltage GaN-on-SiC HEMTs is studied. Here, severe
degradation of dynamic RON characteristics due to the induced creation of traps with relatively short time
constants is discussed in detail. The results emphasize the importance of characterizing dynamic
RON
or
current collapse characteristics over a very short time scale in electrical stress experiments.
In chapter 4, the current collapse phenomenon in high-voltage GaN-on-Si MIS (Metal-InsulatorSemiconductor) HEMTs designed for > 600 V operation is investigated. Device structures featuring
multiple field plate structures and a gate dielectric which are different from the device studied in the
previous chapters are discussed in detail. In order to handle the very high operational voltage of this
device along with monitoring the current collapse precisely, a unique automatic characterization/stress
measurement environment has been developed. From electrical stress experiments in the OFF-state, we
have observed trapping that is so severe that leads to total current collapse such that the device effectively
behaves as an "open" when subsequently biased in the ON-state. The recoverability and repeatability of
this phenomenon and the impact of device geometry and temperature have been investigated in great
detail. Based on many experiments, we postulate a responsible mechanism which consists of electron
trapping inside the AlGaN/GaN heterostructure that takes place through a tunneling process under highelectric-field.
Finally, in chapter 5 the conclusions and suggestions from our research are presented. Ways to
mitigate dynamic ON-resistance phenomenon are suggested. We also propose suggestions for future work.
1.5.
References
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26
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null-null, 2012.
27
[20] G. Meneghesso, G. Verzellesi, R. Pierobon, F. Rampazzo, A. Chini, U. K. Mishra, C. Canali, and E.
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Dynamic On-Resistance Increase and Gate Charge Measurements in High-Voltage GaN-HEMTs
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(ISPSD), 2012, pp. 333-336.
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GaN HEMTs," Microelectron. Reliab., vol. 52, no. 12, pp. 2875-2879, Dec. 2012.
[24]M. Meneghini, A. Stocco, R. Silvestri, N. Ronchi, G. Meneghesso, and E. Zanoni, "Impact of hot
electrons on the reliability of AlGaN/GaN High Electron Mobility Transistors," in Reliability Physics
Symposium (IRPS), 2012 IEEE International,2012, pp. 2C.2.1-2C.2.5.
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effects, surface states, and the source of electrons in AlGaN/GaN heterostructure field effect
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surface passivation on the microwave characteristics of undoped AlGaN/GaN HEMTs," IEEE
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Mimura, "A comparative study of effects of SiNx deposition method on AlGaN/GaN heterostructure
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"Passivation of AlGaN/GaN heterostructures with silicon nitride for insulated gate transistors," in
2000 IEEE/Cornell Conference on High Performance Devices, 2000. Proceedings, 2000, pp. 208-
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"Mechanisms of RF Current Collapse in AlGaN GaN High Electron Mobility Transistors," IEEE
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233508-233508-3,Jun.2012.
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28
29
Chapter 2. Dynamic ON-resistance in high-voltage GaN-onSiC HEMTs
2.1.
Introduction
In the previous chapter, the great potential of GaN power transistors for improved power
switching performance was discussed. In this chapter, dynamic ON-resistance
(RON)
or current collapse
phenomenon is investigated in greater detail by proposing and demonstrating a new measurement
methodology.
Among several technical requirements in an efficient power switch, a critical one is obtaining a
very low RON immediately after switching from a high-voltage OFF-state to a low-voltage ON-state. As
discussed in chapter 1, in the more mature RF power GaN HEMTs, dynamic switching problems or
current collapse has been often present and detracts from RF power performance [1], [2]. These issues
have also been observed in power switching applications [3], [4] but are much less understood.
Towards the goal of achieving fundamental understanding of this problem, we have developed a
new dynamic
RON
transient measurement methodology which allows the observation of
RON
transients
after a switching event over a time period that can span many decades. The technique combines
measurements from two different instruments. The acquired dynamic
using a current-transient methodology recently developed [4].
30
RON
transients are then analyzed
We demonstrate the usefulness of this approach by carrying out a systematic study of dynamic
RON
on high-voltage GaN HEMTs on SiC substrate as a function of time, temperature and pulse
conditions. In the samples that we have investigated, we find that after biasing at an OFF-state voltage the
initial dynamic value of RON increases as the voltage increases. Also, on a short time scale, we find that
RON recovers in a temperature independent manner. In contrast, on a longer time scale, the RON transients
are found to be thermally activated.
We propose that the fast recovery behavior takes place through an electron tunneling process
from traps located inside the AlGaN barrier close to the GaN channel layer. Likely candidates are
interface states at the AlN spacer/AIGaN barrier interface. The slower thermally-activated recovery is
attributed to traps in the AlGaN or at the surface.
This work provides a methodology towards understanding and mitigating dynamic RON issues in
high-voltage GaN FETs. This chapter is organized as follows. First, the measurement technique is
explained in details. Next, the devices used to illustrate the technique are briefly described and detailed
results obtained under different conditions are presented. The importance of epitaxial growth details on
dynamic
RON
is illustrated. Lastly we hypothesize the physical origin of the trapping behavior that is
observed.
2.2. Proposed dynamic ON-resistance measurement technique
The dynamic RON measurement technique that we have developed is capable of collecting
RON
transients from 200 ns to any arbitrary length of time. For this we use two different instruments: an
Auriga AU4750 pulsed IV system for
RON
semiconductor device analyzer (SDA) for
transients from 200 ns to 3 ms and an Agilent B1500A
RON
transients beyond 3 ins. In both cases, synchronous
switching of VGS and VDS is performed.
31
OFF (VGSQ= -10 V, VDSQ= 50 V) to ON
1D(2 00 ns t 3 MS)
@ VGS= 1 V, VDS 1.2
0.08
0.08
.D(t=
0.06
1 Ms) @ VGS= 1 V
0.06
P
E
0.04-5
E
E
E
--
0
10 ps
0.04
200 ns
e0
-
0.02-
0.02-o
040
0
PS
0
1/RON
1
2
Time [sec]
3
x 10-1
0
0.4
0.8
V0
D [IV]
1.2
Figure 2-1. ID waveform measured by pulsed IV system. The device is synchronously
switched from an OFF-state quiescent bias of VGSQ=-10 V, VDsQ=50 V to an ON-state of VGs=l V
and VDs changing from 50 mV to 1.2 V at ambient temperature of 25 *C. Through the simultaneous
measurement of both ID(t) and VDs(t) transients in the linear regime, the instantaneous RON( 2 00 ns
<t < 3 ms) is extracted as shown on the right.
With the pulsed IV system, we successively switch from an OFF-state quiescent (Q) bias to an
ON state given by VGs=l V and several VDS values in the linear regime of device operation (<1.2 V). In
this manner, we measure the linear drain current characteristics close to the origin. Figure 2-1 shows a
typical measured ID waveform in a high-voltage GaN HEMT after it is switched from an OFF-state
(VGSQ= -10 V, VDSQ= 50 V) to the ON-state. ID(t) and VDS(t) are measured every 200 ns within a pulse
width of 3 ms and a duty cycle of 10%. For each data point, the measurement time is 5 ns. To minimize
noise and enhance measurement accuracy, each extracted data point represents an average of 300
measurements. As a result of heavy electron trapping that occurs during the OFF-state period, ON-state ID
in the linear regime shows a very slow increase in time towards the expected DC value. In addition, since
the pulsed IV system itself has an internal source resistance, as the device RON decreases, the range of VDS
values in the ON state decreases accordingly. Through the simultaneous measurement of both ID(t) and
32
0
VDs(t) transients in the linear regime (Figure 2-1 right), the instantaneous RON(20 ns < t < 3 ms) can be
extracted.
9
Semiconductor
Device Analyzer
Pulsed IV
8E
z
0
6RON DC= 5.2 Q mm
10-7 1~7110-1014 10-1072 101 1 00 101 102 103
Time [sec]
Figure 2-2. RON transients from 200 ns up to 1,000 s on GaN-on-SiC high voltage HEMTs
from an OFF-state (VGSQ=-5 V, VDSQ= 4 0 V) to ON-state switching at ambient temperature of 55 'C.
Blue line is obtained from pulsed IV system (Auriga AU4750) and red line from semiconductor
device analyzer (Agilent B1500A). Also shown is the DC values of RON obtained after fully
detrapping the device (marked as RON_Dc). This shows 66% higher RON at 200 ns than in DC.
RON
transients for longer time periods can be explored using the SDA. The synchronous pulsed
mode of the B 1500A allows the continuous measurement of the RON transient from 3 ms to any arbitrary
time. In contrast to the pulsed IV system, B1500A can measure ID(t) transients at a constant VDs value
(0.5 V has been used here). By adjusting the time that the device resides in the OFF state, one can closely
match the beginning of the transient as measured by the SDA with the end point of the transient
measurement obtained by the pulsed I-V system and obtain a complete transient that spans many decades
in time. One example is shown in Figure 2-2 for transients obtained over 10 decades in time. The blue
33
line is measured from the pulsed IV system and the red one comes from SDA. Also shown is the DC
value of RON obtained after fully detrapping the device under visible light illumination.
In these synchronous pulsed measurements using the pulsed I-V system and the SDA, fast
switching of
VGs
and VDS is important so as to prevent the occurrence of a momentary high power state
during the transition ("hard" switching). Figure 2-3 shows waveforms of three different switching events
from the OFF state (VGSQ= -5 V, VDSQ= 40 V) to the ON state in one of our test samples. These
measurements are obtained through the pulsed I-V system. In one event, the pulsing of
VDS
and VGS is
synchronous. In the other two events, a delay of 200 ns or 400 ns is introduced between the switching off
of
VDS
and the switching on of VGS. The corresponding RON transient measurements are shown below.
The time lapse between samples in the waveforms at the top of Figure 2-3 is 5 ns. With our
relatively small size devices, when tested through the pulsed I-V system, a fast slew late of 1 V/ns is
measured. In the synchronous case, this results in a very short overlap (a few ns) of the VDS and VGS
waveforms at relatively low values of
VDS.
This does not introduce any visible trapping in the device as
evidenced by the resulting RON transients which are essentially identical to those obtained when a delay of
200 ns or 400 ns is introduced between the two pulses. The situation might be different in the case of
large size devices where the slew rate can be significantly slower and an adjustment of the delay time
between VDS and VGS pulses might be needed.
In the synchronous pulse mode of the B 1500A, there is no way to control the relative delay
between the gate and drain pulses. However, since the switching occurs on a much slower time scale and
we always observe a good match of characteristics at the boundary with the data acquired from the pulsed
I-V system, we conclude that any hard switching that might occur results in negligible trapping on the
time scale in which we use this tool (t>3 ms).
34
45
2
40
1
35
VDS(t)
30
400 ns 200 ns
offset offset
25
VDsMt
VGSM
0
-1
20
-2
VT
15
-3
Synchronous
10
-4
VDSt
5
-5
0
0
-5
0.2
0.6
0.4
Time (ps)
0.8
1
-6
8
OFF (-5 V, 40 V) to ON @ T= 25 C
7.5
400 ns
off set
E
7
0
VDS t
200 n s
offset
0
Synchronous
6.5
VDS
I
107
-4
-5
10,
It)
104
10Time [sec]
1 0-2
Figure 2-3. Top: VDs and VGS waveforms of three switching events from an OFF state
-5 V, VDsQ= 40 V) to the ON state. In one event, the pulsing is synchronous. In the other two,
a delay of 200 ns or 400 ns is introduced between the falling edge of VDS and the rising edge of VGS.
Bottom: resulting RON transients are unaffected by the relative alignment of the VDs and VGs pulses
indicating that trapping during the transient is negligible. In our relatively small size devices, a fast
slew late of 1 V/ns is obtained.
(VGSQ=
35
The stitching approach illustrated in Figure 2-2 is time consuming and inevitably leaves a small
residual discrepancy between the measurements obtained through the two techniques at the 3 ms stitching
point. This can cause noise in the final time constant spectra [4]. We have eliminated this problem by
appropriately scaling the transient data obtained from the SDA. Figure 2-4 shows how this scaling works.
We show here RON transients obtained with the pulsed IV system, as specified above, and the SDA. Both
sets of transients are obtained with the device at the same OFF state bias point. Before the SDA
measurements, the device is kept in the OFF-state for 50, 75, or 100 sec. All of them result in a visible
mismatch with the pulsed IV data. As the OFF-state time increases, the initial value of
RON
at 3 ms
increases due to higher electron trapping. The evolution of the transient beyond that initial point, however,
is independent of this initial value. This can be seen in the bottom of Figure 2-4 that graphs (RON(t)
RONDC)/
(RON(t=3 ms) -
RON_DC)
-
for the three cases. As seen, the transients closely overlap each other.
This suggests that the RON transients are largely independent of the initial value of RON at 3 ms and that
simple scaling can be used to stitch the RON measurements obtained from the SDA to those derived from
the pulsed-IV system.
From this study, we have synthesized the following approach to obtain complete RON transients.
First, an RON transient is obtained using the pulsed IV system. Then, the OFF-state time in the B 1500A is
controlled to produce an
RON
transient that closely matches the final value obtained from the pulsed I-V
system. The residual mismatch is resolved through scaling of the B 1500A data set to match with the
pulsed I-V data at t=3 ms. The overall transient is then analyzed using the time constant spectrum
approach of [4].
36
OFF (-5 V, 40 V) to ON @ T= 25 C
9
-
Pulsed IV
L
-
-I
SDA
I
I
-I
100 sec
8
50 sec1
E
E
z 6
0
a:
RON DC
-6
-5
-4
-3
102
-1
10
10
102
Time [sec]
'
1.2 ,
E
CO
z
1
1 1 1
l
1
0.8-
0
0.6-
z
0.4-
0
0.21-10
102
106
10
101
102
Time [sec]
Figure 2-4. Top:
RON
transients in OFF(VGsQ= -5 V, VDSQ= 40 V) to ON-state switching
from pulsed IV in the blue line and from SDA using different OFF-state times of 50, 75, or 100 sec.
A visible mismatch occurs with the pulsed IV data. Scaling the SDA-obtained data so as to match
ARON(t)/ARON(3ms) makes all lines overlap each other as shown in dotted line. The bottom one
shows identical normalized RON recovery rates suggesting that the RON transients are largely
independent of the initial value of RON(3ms).
37
2.3.
Experimental demonstration on GaN-on-SiC HEMTs
8.5
87.57E
E
60 6.5 z
cr
65.5-
4.5
10~
RON DC 4.6 -mm
1
0
1
2
3
10-6 10~5 10-4 10-3 10- 10- 101 10 102 101
Time [sec]
104
Figure 2-5. Complete dynamic RON transients from 200 ns up to 10,000 s over 11 decades of
time period through our proposed technique in the section 2.2. It has been obtained on GaN-on-SiC
high voltage HEMTs from an OFF-state (VGSQ=-5 V, VDSQ= 4 0 V) to ON-state switching at ambient
temperature of 25 'C.
We have demonstrated the usefulness of our proposed dynamic
RON
technique by studying in
detail industrially prototyped AlGaN/GaN HEMTs grown by MOCVD on SiC for S-band power
amplifier application. The heterostructure includes a GaN cap and an AlN spacer. The device design
features an integrated field plate and a source-connected field plate. The gate width is 6x100 pm. The
devices are depletion mode with threshold voltage around -3 V. The breakdown voltage of the devices is
around 160 V. All measurements are performed in the dark and in air. There was no discernible
permanent degradation of the devices as a result of repeated testing under the conditions used in this work.
Figure 2-5 shows complete dynamic
RON
transients from representative devices through our
proposed technique when the device is switched from an OFF-state with VGSQ=-5 V and VDSQ= 4 0 V at T=
25 'C. This has been obtained from 200 ns up to 10,000 s over 11 decades of time. RON at 200 ns is about
38
73% higher than in DC
(RONDC).
Such a high dynamic RON represents a big problem for power switching
applications. The pattern of recovery of RON exhibits a very slow-transient in the s-ks time range.
In order to gain insight into the physics of this dynamic behavior, we have carried out OFF to ON
transients from different quiescent VDS values at ambient temperature, as shown in Figure 2-6. As VDSQ
increases, the dynamic
RON
increases in a prominent manner presumably as a result of the increased
extension of the high-field region into the drain.
The dominant time constants underlying these transients can be obtained using a time constant
spectrum analysis [4]. We use a sum of exponentials with 20 time constants per decade within the range
from 10- 7 sec to 103 sec. Examples of fits are shown at the top of Figure 2-6 and the resulting time
constant spectra are shown on the bottom of this figure.
These indicate that there are multiple time
constants with values that do not change as the applied electric field in the OFF-state increases. Only the
magnitudes of the signals are affected by increasing VDSQ. In particular, there are two prominent time
constants in the 10 to 1000 s range and some more in the sub-ps to ms range. All get more prominent as
VDSQ increases. There is also a time constant around 50 ms that prominently increases when VDSQ > 100 V.
This could be due to the depletion region sweeping through a particular defect at high values of VDsQ.
39
16
VGSQ= -10 V
VDSQ= 125 V~
14
T
o Exp
12
100 V
10
75 V
z
0
-- Fitting
8
50 V
6
--------..----.-.---
25 V
10
-1 10
RON
10-4 10-3 10- 10
DC
101 101 102 103
t (sec)
125 V
O.5
0.4
V
At100V
0.3
75V
-
E
0.2
0.1
50 V
t
25V
^1
-6
-T-4
-3
C -7
10 10 10 104 10-3 10- 10-1 10
10
102 103
t [sec]
Figure 2-6. Top: Dynamic RON transients after OFF to ON switching events from different
quiescent VDs conditions from VDSQ= 2 5 V up to 125 V in 25 V increments at ambient temperature
of 25 *C. Red dots are measurements and blues lines are fitting curves through a sum of
exponential terms with time constants ranging from 10,s to 10 3s as shown in the bottom. The device
exhibits prominent time constants in the 10 to 1000 s range and some in the sub-ps to ms range. As
VOFF increases, the dynamic RON increases too but the time constants do not change.
40
1.8
VGSQ=-5V, VDSQ=40 V
1.6
T= 25 C
0
W 1.4
65
0
1854
1.27
10 10
-10
1
10 104 10 10
10
10 101 102 10,
Time [sec]
0.5
T= 185 C
~0.4
145 C
S0.3
-'
-. 0.2
105 C
.a
A
E
65C
0.1
02
10
10~6 1015 10103 10-2 10
T
100 10
102 103
[sec]
5
Figure 2-7 Top: RON/RONDC transients at different ambient temperatures for VGSQ=- V and
VDsQ= 4 0 V. The resulting time constant spectra (bottom) clearly indicate that the dominant
transients for long times substantially speed up as the temperature increases whereas short time
constants are independent of temperature.
41
In order to further the understanding of the physical processes behind these transients, we have
performed dynamic RON measurements at different ambient temperatures and their time constant spectra
have been derived as presented in Figure 2-7. In this figure, the dominant transients substantially speed up
as the temperature is increased. The time constant spectra at different temperatures show this acceleration
very clearly. Dynamic RON at 200 ns shows slightly negative dependence as the temperature increases.
This is most likely due to the high voltage trapping process resulting in less trapping as the temperature
increases since in the OFF state, there is always a counterbalancing detrapping process that is enhanced.
In addition to this, the device also exhibits fast transients that change little with temperature. This
temperature independent behavior for short times is also verified in the corresponding spectra.
20
0.65 eV..**
15
0.82 e.V.--
A-'A*..
.0.76
10
eV
.
0
~.
0.57 eV+
*...---
...........
*.
-5
23
28
33
38
43
1/kT [eV-1]
Figure 2-8. Arrhenius plot of time constant spectrum of Figure 2-7. The size of the symbols
is proportional to the height of the time constant peak. Dominant traps at 0.79 eV, 0.82 eV, and 0.76
eV are identified. A set of short time constants which are independent of temperature are also
observed. They are responsible for the fast transients.
42
Following the methodology of [4], we have plotted the evolution of the dominant time constants
with temperature in an Arrhenius plot (Figure 2-8). The size of the symbols in this figure is proportional
to the height of the time constant peaks. From this Arrhenius plot, two distinct patterns emerge: a set of
long time constants with thermally activated behavior and another set of short time constants that are
independent of temperature. The long thermally-activated time constants can be associated with
conventional traps. The dominant traps are estimated at 0.79 eV, 0.82 eV, and 0.76 eV below the
conduction band edge. Traps at similar energies have been reported by other authors in similar structures
[5]-[7].
To further clarify the physics, we have also performed high-power (HP) to ON transients. Figure
2-8 illustrates dynamic
RON
transients from a quiescent bias of VGs=2 V, VDs=7 V and their respective
time constant spectra at different ambient temperatures. The power level was 5.4 W/mm at ambient
temperature of 25 'C corresponding to the red line. The transients are dominated by fast time constants
only. In contrast with the data in Figures 2-6 and 2-7, there are no slow thermally-activated transients
present. Furthermore, the dominant time constants of the transients in Figure 2-9 are temperature
independent as the spectrum clearly reveals. The initial value of
RON/RON-DC
at 200 ns decreases with
temperature again reflecting a competition between trapping and detrapping during the HP trapping state.
These temperature independent and fast recovery characteristics support the notion that the fast time
constant processes that are observed in Figures. 2-6, 2-7 and 2-9 have a common origin.
We have also performed additional HP-to-ON transients at different VDG values but the same
power dissipation as shown in Figure 2-10. These reveal that the fast transients are not related to thermal
cooling of the device but are strongly enhanced by the quiescent voltage VDGQ. In fact, RON at 200 ns
follows a hot electron type law as shown on the right of Figure 2-10 suggesting that the electrons that are
released during these fast transients became trapped after acquiring kinetic energy from the high field in
43
the channel. Hot-electron phenomena have been also prominently observed in several other studies [6],
[8], [9] along with severe impact on RON degradation.
2.5
7 V) to ON
HP(VGSQ-= 2 V, VDS
2 -2
T= 5 C
z
0
CE
z
0
100
1.5
150
1i
II 1,
11,
I
1 , 111-1
10
-6
-5
I
-4
I
I
10- 10
10
I
100 10
10 103
Time [sec]
0.
4
T= 150 C
0. 4
- j
100 C
0.
50 C
0
0. 2
%
E
25 C
4 nw\
0.
5-5 C
3
10~7 10~ 10-5 104 10-1 10- 10- 10
,T
10
10
10
[sec]
Figure 2-9. High power to ON-state transients at different ambient temperatures and the
resulting time constant spectra (inset). The high power state bias is VGsQ= 2 V and VDsQ= 7 V (the
power level was 5.4 W/mm at ambient temperature of 25 'C corresponding to the red line). The
transients are dominated by temperature-independent fast time constants. No thermally activated
slow-transients are observed.
44
14
vvmri4
-.
12
>I
35
E3
Pio.
cc 0 8
E1
VDGQ=
2
V ~
2100
>
2.E1.5
1 V.
6
1 10
1
5
1
1
"
3 5V0V
2
0.06
1/(VDG+V-r)
0.08
0.1
[V]
Time [sec]
Figure 2-10. HP to ON transients from quiescent points at different VoG but with the same
power dissipation. Dynamic RON at 200 ns increases eXponential following a hot-electron type law as
shown in the right.
2.4.
Impact of epitaxial growth on dynamic ON-resistance
We have studied the importance of epitaxial growth details on dynamic RON characteristics by
applying our methodology to identical devices fabricated on a "nominally" identical epitaxial wafer that
was grown by a different commercial epitaxial vendor. The device layer stack comprising the GaN cap,
AlGaN barrier, AlN spacer and GaN channel layer follows an identical design with the same AlGaN mole
fraction and thicknesses. Most likely, there are differences in the buffer structure design which is
proprietary information of each epitaxy-growth supplier and is unknown to us. This alternative wafer was
processed into devices in the same lot with the same layout as the sample discussed earlier in this thesis.
The breakdown voltage of these new devices is higher than 200 V.
A different buffer could well result in a different defect structure in the top active layers that
produce different dynamic RON characteristics as evaluated by our methodology. As is the case for the
45
wafer discussed above, many different devices have been tested and the results have been consistent. The
observed differences shown here between devices from the two wafers reflect wafer to wafer differences.
Dynamic
RON
transients under identical OFF to ON switching conditions as in Figure 2-6 have
been measured in a device from this alternative wafer at ambient temperature of 25 'C and are shown in
Figure 2-11. The observed pattern of RON recovery is rather different from those shown earlier. In contrast
to the dominance of long time constants in the data of Figure 2-6, the alternative wafer exhibits much
weaker time constants for longer time periods whereas the short time constants in the sub-ps to ms range
dominate. This is clearly seen in the time constant spectra shown in the Figure 2-11. These measurements
show that these two wafers have a rather different defect structure.
Dynamic RON measurements at different ambient temperatures following trapping at VGSQ=- 5 V
and VDSQ= 40 V in the alternative wafer are shown in Figure 2-12. These data are equivalent to those of
Figure 2-7 earlier in this thesis. Once again we find that the recovery transients with short time constants
change little with temperature. This temperature independent behavior is also verified in the
corresponding spectra in the bottom of Figure 2-12.
46
12
VGSQ= -10 V
VDSQ=1
10
E
E
8-
V
25
o Exp
0
""-
7
z
Fitting
6
0
4-
25
RON DC
2)
10 - 10-10710
1
-2
-3
-1
10 10 102 10
t (sec)
0 .5
125 V
0.
100 V
E 0.
3T%
75 V
E
U.
-4-
-
0.1
3
-
50 V
At
25 V
OIP
-2
10-1
10 -7 101 10- 10-4
t
10
10
102 103
[sec]
Figure 2-11. Top: dynamic RON transients in the alternative wafer (see text) after identical
OFF to ON switching events as in Figure 2-6 at ambient temperature of 25 'C. The bottom shows
the corresponding time-constant spectra. In contrast to Figure 2-6, devices in this wafer have much
weaker time constants in the longer time periods whereas short time constants in the sub-ps to ms
range dominate and do not change as VOFF increases.
47
2.5
VGSQ= -5 V, VDSQ= 40 V
2F
45
0
8
105
0
It
1.5F
65
T= 25 C
10-
-6>
-5
104 10-10-2 10-1 10
Time [sec]
10
102 106
0.8
T= 185 C
0.6
~
0.4
T
145 C
V
-E-
E
105 C
0.2
0
10 10 10 10 10 10 10
t [sec]
10
10 10 10
Figure 2-12. Top: RON/RON _DC transients in devices from the alternative wafer at different
ambient temperatures for VGSQ=-5 V and VDSQ= 4 0 V. The resulting time constant spectra (bottom)
show that the dominant transients with short time constants are temperature-independent.
An Arrhenius plot for the dominant time constants of Figure 2-12 is shown in Figure 2-13. As in
Figure 2-8, the size of the symbols indicates the magnitude of the corresponding time constant. In this
48
alternative wafer, a richer spectrum of traps with energies between 0.57 and 1.12 eV is observed but their
concentration is much lower than in Figure 2-8. The short time constants are clearly dominant in this
wafer and they are again temperature independent.
These results reveal that there are at least two distinct mechanisms that dominate dynamic
RON
transients at short times and at long times. The long time transients are associated with conventional traps.
The noticeable differences in the two wafers indicate that these can be engineered through proper growth
protocols. The short time transients arise from a different mechanism and both wafers suffer from it. This
suggests that they might be associated with an intrinsic aspect of the heterostructure.
20
1.05 eV
1.12 eV
10 ~
.. N*
0.72 eV
.
.
..
0. 85 eV
+.4
*.SON
*ai
0
4-00
CM
10
.. 00.*
-5
23
28
33
38
43
1/kT [eV-1]
Figure 2-13. Arrhenius plot of time constant spectrua of Figure 2-12. The size of the
symbols is proportional to the height of the time constant peak. A rich spectrum of traps with
activation energies between 0.57 eV and 1.12 eV is observed but their concentration is much lower
than that in Figure 2-8. The dominant time constants are short and do not exhibit any temperature
dependence.
49
2.5. Mechanisms responsible for dynamic ON-resistance
Our methodology when applied to GaN HEMTs on SiC reveals a rich dynamic behavior of
RON-
A picture that can explain all the experimental observations described above is illustrated in Figure 2-14.
In the OFF state, electrons are trapped as they flow out the gate into the AlGaN barrier and eventually
into the channel (Figure 2-14 left). These electrons can be trapped inside the AlGaN, at the surface or at
interface states at the AlGaN/AlN interface right above the channel [10]. In the HP state on the other hand,
electrons in the channel gain kinetic energy and overcome the energy barrier with the AlGaN and get
trapped. Possible sites for this trapping process are interface states at the AlGaN/AlN interface right
above the channel (Figure 2-14 middle).
During the detrapping process that follows OFF state biasing we observe fast temperatureindependent detrapping processes as well as long thermally-activated detrapping processes. On the other
hand, after HP state trapping, only fast temperature-independent detrapping is observed. This suggests
that the fast processes observed in both cases have the same origin and that detrapping takes place
through a tunneling process. This is consistent with detrapping from interface states at the AlGaN/AIN
spacer interface [10], [11]. Traps that are physically located behind a barrier but very close to the channel
and that release their electrons through a tunneling process are known as border traps [12]. We postulate
that AlGaN/AlN interface states behave as border traps as the AlN layer is very thin. The longer
thermally-activated time transients observed after OFF state trapping are associated with conventional
traps at the surface on the gate-drain gap or inside the AlGaN barrier. These are accessible from the gate
in the OFF state but not from the channel in the high-power state because of the relatively large electric
field across the AlGaN barrier.
The defects at the AlGaN/AiN interface are perhaps intrinsic to the nature of this interface and the
high stress under which the AlN is grown. If our hypothesis is correct, this detrapping mechanism could
be eliminated through removal of the AlN spacer layer.
50
slow detrapping from
surface or barrier traps
detrapping
from border traps
_____fast
GaN AIGaN AIN GaN
electron trapping
in the OFF state
hot-electron trapping
in the HP state
electron detrapping
in the ON state
Figure 2-14. Postulated mechanisms responsible for dynamic RON of GaN HEMTs observed
in this work. In the OFF state, electron trapping at the surface, in the AlGaN and at the AlGaN/AIN
interface takes place as electrons flow out the gate. In the HP state, hot electrons from the channel
are trapped at AlGaN/AlN interface states. In the ON state, electron detrapping takes place
thermally for traps in the AlGaN or at the surface and through a tunneling process for AlGaN/AIN
interface traps (border traps).
Many studies have been devoted to buffer trapping which depends on the various types of traps
that are introduced during the growth process [13]. Some buffer trapping could be present in the devices
that we have studied. Separation of buffer trapping, barrier trapping and surface trapping is an important
topic that is being explored by other techniques [14]. The dynamic
RON
characterization methodology
proposed in this work should also be helpful to study this issue.
2.6.
Conclusions
In summary, we have developed a new methodology to investigate RON transients over arbitrary
lengths of time. We have used this new technique to study trapping effects in high-voltage GaN HEMTs
51
under a variety of pulsing conditions. In OFF-to-ON time transients, dynamic
RON
is enhanced up to
several times the original DC value, particularly as the OFF-state voltage increases. We have identified
two distinct mechanisms with different time scales and temperature behavior. On a short time scale, the
fast release of trapped charge takes place through a temperature-independent tunneling process. We
postulate that interface states at the AlGaN barrier/AlN spacer interface are responsible for this.
Conventional thermally assisted detrapping follows on a longer time scale. This we postulate occurs from
traps at the surface or inside the AlGaN barrier. In contrast, after a High-Power to ON switching, only fast
detrapping through a temperature independent process is observed. This is also consistent with trapping at
the AlGaN/AlN interface. These findings provide a path to engineer a GaN power-switching transistor
with minimum dynamic RON problems.
2.7. References
[1] G. Meneghesso, G. Verzellesi, R. Pierobon, F. Rampazzo, A. Chini, U. K. Mishra, C. Canali,
and E. Zanoni, "Surface-related drain current dispersion effects in AlGaN-GaN HEMTs,"
IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1554-1561, Oct. 2004.
[2] R. Chu, A. Corrion, M. Chen, R. Li, D. Wong, D. Zehnder, B. Hughes, and K. Boutros,
"1200-V Normally Off GaN-on-Si Field-Effect Transistors With Low Dynamic on Resistance," IEEE Electron Device Lett., vol. 32, no. 5, pp. 632-634, 2011.
[3] M. Faqir, G. Verzellesi, A. Chini, F. Fantini, F. Danesin, G. Meneghesso, E. Zanoni, and C.
Dua, "Mechanisms of RF Current Collapse in AlGaN GaN High Electron Mobility
Transistors," IEEE Trans. Device Mater. Reliab., vol. 8, no. 2, pp. 240-247, Jun. 2008.
[4] J. Joh and J. A. del Alamo, "A Current-Transient Methodology for Trap Analysis for GaN
High Electron Mobility Transistors," IEEE Trans. Electron Devices, vol. 58, no. 1, pp. 132-
140, Jan. 2011.
[5] A. R. Arehart, A. Sasikumar, G. D. Via, B. Winningham, B. Poling, E. Heller, and S. A.
Ringel, "Spatially-discriminating trap characterization methods for HEMTs and their
application to RF-stressed AlGaN/GaN HEMTs," in Electron Devices Meeting (IEDM),
2010 IEEE International,2010, pp. 20.1.1-20.1.4.
[6] D. Jin and J. A. del Alamo, "Impact of high-power stress on dynamic ON-resistance of high-
voltage GaN HEMTs," Microelectron.Reliab., vol. 52, no. 12, pp. 2875-2879, Dec. 2012.
[7] A. R. Arehart, A. Sasikumar, S. Rajan, G. D. Via, B. Poling, B. Winningham, E. R. Heller, D.
Brown, Y. Pei, F. Recht, U. K. Mishra, and S. A. Ringel, "Direct observation of 0.57 eV
trap-related RF output power reduction in AlGaN/GaN high electron mobility transistors,"
Solid-State Electron., vol. 80, pp. 19-22, Feb. 2013.
52
[8] N. Killat, M. Tapajna, M. Faqir, T. Palacios, and M. Kuball, "Evidence for impact ionisation
in AlGaN/GaN HEMTs with InGaN back-barrier," Electron. Lett., vol. 47, no. 6, pp. 405406, Mar. 2011.
[9] M. Meneghini, A. Stocco, R. Silvestri, G. Meneghesso, and E. Zanoni, "Degradation of
AlGaN/GaN high electron mobility transistors related to hot electrons," Appl. Phys. Lett., vol.
100, no. 23, pp. 233508-233508-3, Jun. 2012.
[10] S. A. Vitusevich, 0. A. Antoniuk, M. V. Petrychuk, S. V. Danylyuk, A. M. Kurakin, A. E.
Belyaev, and N. Klein, "Low-frequency noise in AlGaN/GaN HEMT structures with AlN
thin film layer," Phys. Status Solidi C, vol. 3, no. 6, pp. 2329-2332, 2006.
[11]
S. Huang, Q. Jiang, S. Yang, Z. Tang, and K. J. Chen, "Mechanism of PEALD-Grown
AlN Passivation for AlGaN/GaN HEMTs: Compensation of Interface Traps by Polarization
Charges," IEEE Electron Device Lett., vol. 34, no. 2, pp. 193-195, Feb. 2013.
[12]
D. M. Fleetwood, M. R. Shaneyfelt, and J. R. Schwank, "Estimating oxide-trap,
interface-trap, and border-trap charge densities in metal-oxide-semiconductor transistors,"
Appl. Phys. Lett., vol. 64, no. 15, pp. 1965-1967, Apr. 1994.
M. J. Uren, J. Moreke, and M. Kuball, "Buffer Design to Minimize Current Collapse in
[13]
GaN/AlGaN HFETs," IEEE Trans. Electron Devices, vol. 59, no. 12, pp. 3327-3333, Dec.
2012.
[14]
D. W. Cardwell, A. R. Arehart, C. Poblenz, Y. Pei, J. S. Speck, U. K. Mishra, S. A.
Ringel, and J. P. Pelz, "Nm-scale measurements of fast surface potential transients in an
AlGaN/GaN high electron mobility transistor," Appl. Phys. Lett., vol. 100, no. 19, pp.
193507-193507-4, May 2012.
53
54
Chapter 3. Impact of high-power stress on dynamic ONresistance of high-voltage GaN-on-SiC HEMTs
3.1.
Introduction
In the previous chapter, we have developed a new measurement methodology for dynamic
RON
phenomenon or current collapse characteristics and applied this new technique to analyze the intrinsic
dynamic RON of high voltage GaN-on-SiC HEMTs in great detail.
Hard-switching
RE load line
IDA
.............
.......
0
ON ......
........
......
................
V DS
OFF
VDS
Figure 3-1. The operational regions in the RF power amplifier (left) and the powerswitching devices (right) are described. The expanded RF load line (left) and the hard-switching
operation (right) undergo high-power state continuously which can degrade the device performance.
55
In this chapter, by using this technique, we aim to achieve further understanding in the
degradation of dynamic RON characteristics as a result of electrical stress of GaN transistors. In particular,
we study here the impact of high-power stress on dynamic
RON-
In the operational domain of GaN
transistors for both power-switching and RF power amplifier applications, the devices can frequently
experience very high power state as shown in Figure 3-1 which describes the expanded load line in the RF
power amplifier and the trajectory of power switching operation in the hard-switching mode. It clearly
shows that the accumulated stress from high power state operation can be problematic to the reliability of
GaN transistors as well as dynamic RON characteristics. However, there is much less understanding about
these issues [1].
Using our newly proposed technique discussed in the chapter 2, we study here the impact of highpower (HP) stress on dynamic
RON-
We find that HP-stress results in much worsened dynamic RON in the
sub-ms range, that is, RON increases several fold in a short time scale after an OFF-ON switching event.
This occurs as a result of the stress-induced creation of traps with relatively short time constants. On a
longer time scale, negligible degradation of dynamic
RON
is observed. These findings suggest that
accumulated device operation that reaches out to the HP state under RF power or hard-switching
conditions can result in undesirable degradation of dynamic
RON
on a short time scale. Our results
highlight the importance of characterizing electrically stress-induced dynamic RON and current collapse
over very short time scales.
3.2.
Experiments
In this study, we have characterized research prototype AlGaN/GaN HEMTs from an industrial
partner fabricated on a heterostructure that has been grown by MOCVD on SiC. These devices are
identical to the ones investigated in the section 2.4 of the previous chapter. The heterostructure includes a
GaN cap and an AlN spacer between the AlGaN barrier and the GaN channel. The devices feature an
56
integrated field plate and a source-connected field plate and exhibit a breakdown voltage higher than 200
V. We have stressed these devices in the high-power state with VGS= 2 V
(ID
0.6 A/mm) and VDs= 20 V
at room temperature which generates a power level of around 12 W/mm. The channel temperature during
the stress is estimated to be around 380 'C. This is a very harsh stress condition designed to accelerate the
rate of degradation. We interrupt the stress every minute and characterize the evolution of important DC
figures of merits such as RON, maximum drain current (IDMAX), and gate leakage current (MGOF) using a
benign characterization suite [2]. Dynamic
RON
is also investigated using our newly proposed
methodology [3] discussed in the chapter 2. We have applied this method to five identical test devices
fabricated on the same chip before and after HP-stress times of 0, 10, 20, 30 and 40 mins.
100
1.2
'1.1
R ON
o
10
E
DMAX
E
00.9
1
~0.8
0
00
I
GOFF
0.7
0.1
0.6
0
30
20
10
High power ON-state stress time [min]
40
Figure 3-2. Time evolution of DC RON, IDMAX (normalized to their initial values) and IIGOFFI
during a constant HP-state stress in GaN HEMTs. RON is defined by the inverse of the linear drain
current measured at VGS= 1 V and VDS= 0.5 V and IDMAX is defined at VGs= 2 V and VDS= 8 V. IGOFF
is the gate leakage current measured at VGS= -5 V and VDS= 0.1 V. The stress conditions are VGS= 2
V and VDs= 20 V. Up to about 30 min of stress, the device characteristics show minor changes.
Beyond 30 min, prominent degradation in both RON and IDMAx and minor one in IIGOFF are
observed.
57
Figure 3-2 plots the time evolution of DC
as
IGOFF
RON
and
lDMAX
normalized to their initial values as well
as a function of stress time for the sample that was stressed for 40 min. The device shows quite
robust characteristics up to 30 min. Beyond this point, significant degradation takes place in
IDMAX
RON
and
while a minor increase in IGOFF is observed. The degradation in RON and lDMAX are mirror images of
each other, suggesting a common origin. The samples stressed for 10, 20 and 30 mins exhibit very minor
degradation in their DC RON and IDMAX values, consistent with the results of Figure 3-2.
Semiconductor
Device Analyzer
rransient from
Pulsed-IV
12
10
OFF (VG 3Q= -10 V, VDSQ= 50 V)
to ON( VGS= 1 V, VDS : 1.2 V)
8
0
0
Czc
6
tstress= 40 min
4
30
2
1
V
10
Virgin
-7 -6
10
-5
10~
-4
10~
-3
10
I
I
I
101 10
10
10
-2
10
-1
1
Time [sec]
Figure 3-3. Dynamic RON transients from 200 ns up to 200 s after OFF (VGSQ= -10 V, VDSQ=
50 V) to ON (VGS= 1 V and VDS < 1.2 V) switching event in different samples that have been subject
to different HP-state stress periods ranging from 0 to 40 min. Up to 30 min of stress, minor changes
in dynamic RON are observed. After 40 min of stress, there is a more than ten-fold increase in
dynamic RON. Very fast RON recovery in the ms range is observed in all cases.
58
Figure 3-3 shows RON recovery transients from 200 ns up to 200 s for all devices after an OFFstate pulse with VGSQ= -10 V and VDSQ= 50 V. From 200 ns up to 3 ms,
RON
is continuously being
measured at VGs= 1 V and VDS < 1.2 V with a duty cycle of 10% in the pulsed IV system. During the rest
of time up to 200 s, RON is being measured using the I-V time sampling mode in the semiconductor device
analyzer after an identical OFF-ON state switching (single pulse) has been applied. In a virgin device,
after this switching event, RON at 200 ns is about 36% higher than in DC (RONDc) and recovers back
within
-10
ms. After HP stress, dynamic RON at 200 ns increases but the recovery takes place on a similar
time scale. After 40 min of stress time, the dynamic RON at 200 ns dramatically increases more than
tenfold over
RONDC.
This is very problematic for both power switching and RF applications.
1I
10
RON/RONDC at 200 ns
0
0
U
5
4
3
2
10 ms
0
0
zr
~
1
i
rONDC1 rON_DCvirgin
0.5
0
10
20
30
40
HP-state stress time [min]
Figure 3-4. Normalized dynamic RON (RON/RONDC) of Figure 3-3 at different times (200 ns,
10 ps, and 10 ms) and RONDC/RONDC virgin (RONDC value in the virgin device) as a function of HPstate stress time in a semilog scale. Dynamic RON mostly increases in a time range from 200 ns up to
a few Ms. RONDC/RONDC virgin shows small increase up to 16% in comparison to dynamic RON
suggesting minor permanent (non-transient) degradation.
59
Figure 3-4 shows dynamic RON (RON/RONDC) at 200 ns, 10 p[s and 10 ms as well as
RONDC/RONDC_virgin (RON_DC value in the virgin device) as a function of stress time in a semilog scale. This
graph leaves clear how dynamic RON increases greatly between 30 and 40 min of stress but only on a time
scale in the ps range. Beyond 10 ms or so, few changes are observed. In addition, RON
DC/RONDC-virgin
shows a small increase up to 16% in comparison to dynamic RON suggesting minor permanent (nontransient) degradation. These findings highlight the importance of selecting an appropriate time scale for
the study of dynamic RON and current collapse in GaN HEMTs after electrical stress.
0.8
RON
+
i
RON 00
40 min
0.6
0.4
E
0.2
20
30
,Virgin,
0
-7
10
10
-6
10
-5
10~
103 10 10~1 10
t [sec]
0
1
10
10
2
103
Figure 3-5. Time-constant spectra for RON transients of Figure 3-3. A sum of exponential
terms with time constant ranging from 100 ns to 1000 s is used to fit the measurement data. The
equation used for fitting is indicated in the inset. The fit yields the ai coefficient corresponding to
each time constant Ti. These data reveal that after 40 min of stress, there is a prominent increase of
the magnitude of transients with short time constants.
60
In order to understand the physical origin of these prominent transients, we have analyzed the
time domain RON data by fitting it with a sum of exponentials (see inset in Figure 3-5) [4]. 20 different
time constants per time decade equally distributed in a logarithmic time scale were used in the fit of every
transient. The amplitude of the various components as a function of their respective time constants is
shown in Figure 3-5. It is clear that after 40 minutes of stress time, fast transients emerge with time
constants in the
sts to ms range.
In contrast, negligible changes occur in the long time constant domain.
12
50-
10
T= 25 C
E
E 30
8
6 0
0
Cc
Q
0z
C:0
6
4
OFF(-10 V, 50 V)
to ON
40-
1
1
.. T
10
0
11
-6, -5 -4 -3) -2)
1-710010101010
~11ic
0 11
-11
2
1010 10210
3
Time [sec]
2
10
7
-6
10~
10
-5
-4
10~
-3
10~
10~
2
10
-
10
0
10
1
10
2
Time [sec]
Figure 3-6. RON/RONDC transients at different temperatures between 25 *C and 150 'C for
VGsQ= -10 V and VDsQ= 50 V after 40 min HP stress. The inset shows the absolute value of the RON
transient. As the temperature goes up, the dominant transients are substantially accelerated. This
suggests that the transients are due to generated traps.
Dynamic RON measurements at different ambient temperatures (T) have been performed with the
goal of illuminating the physical origin of these transients. The inset of Figure 3-6 shows RON transients at
T between 25 'C and 150 0C for the sample that has been subject to 40 min HP stress. As the temperature
61
increases, RONDC increases due to a reduction in mobility. RON at 200 ns, on the other hand, decreases as
electron trapping is mitigated at high temperature. This is more clearly seen in Figure 3-6 that shows the
normalized value of RON over the RONDC value. As the temperature increases, trapping is less severe and
the recovery transient is considerably accelerated.
3.5
-55 C_
-tt
-35 C
t
3
2.5, ci)
C
tt-15
Ao%,
5 C
AM
2
4-.
0~
E 1 101
25C
ILL~A~&SL
-U---
it
65 C
T
1
t
85C-
dOPORRAWAN.-
105 C
0.5
A
"
10
-
125 C_
150 C
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
't[sec]
Figure 3-7. Time-constant spectra for RON transients for temperatures between -55 'C and
150 'C including the transients in Figure 3-6. Arrows with different colors distinguish individual
time constant peaks at different temperatures. Most of them move towards shorter time constants
as the temperature increases indicating a thermally activated behavior.
62
20
0.75 eV
....
EA= 0.87 eV
15
0
0.577eV
eV
-0.53 eV
-
-t404
A5--
~>0
eV
-
----
---
0.31 eV
.23 eV
..
0
-5
25
30
35
40
1/kT [eV-1]
45
50
55
Figure 3-8. Arrhenius plot of time constant spectra from Figure 3-7. The size of the symbols
is proportional to the height of the time constant peaks and the color of them matches that of the
arrows in Figure 3-7. The dominant trap energy levels are located at 0.31, 0.45, 0.53 and 0.57 eV
below the conduction band edge most likely in the AlGaN barrier. These are the traps that are
responsible for the dramatic increase in dynamic RON that is observed in the short time scale.
Figure 3-7 exhibits the time constant spectra extracted from RON transients over a wide
temperature range from -55 'C to 150 *C including transients from Figure 3-6. Arrows with different
colors identify the evolution of individual time constant peaks across temperatures. Most of the time
constants are seen to shorten as temperature increases which suggests that they originate from thermally
assisted electron detrapping from conventional traps (as opposed to traps that communicate with the
channel through a tunneling process [5]-[7]).
The evolution of the dominant time constants with temperature is depicted in an Arrhenius plot in
Figure 3-8. The size of the symbols is proportional to the magnitude of the peak in the time constant
spectra of Figure 3-7. The color of the symbols is also consistent with the arrows in Figure 3-7. The
thermally activated behavior for the time constants that is obtained allows us to conclude that
63
conventional traps are responsible for the increase in dynamic
RON.
Figure 3-8 reveals that the dominant
trap energy levels that have been created as a result of electrical stress have ionization energies of 0.31,
0.45, 0.53 and 0.57 eV. Traps with low energy levels such as 0.23, 0.31, and 0.45 eV appear to have been
generated as a result of the HP-stress whereas deeper traps already existed in the virgin sample but their
density seems to have increased [5]. The observed traps are presumed located below the conduction band
edge of the AlGaN barrier inside its body or at the surface. Similar trap energy levels have also been
reported in similar structures after electrical stress by other authors [8], [9].
3.3. Discussion
5
OFF (-10 V, 50 V) to ON
4F
After 3 min HP-stress with
SVDS= 30 V, P~ 9 W/mm
0)
0
3F
After 20 min HP-stress with
VDs= 20 V, P~ 12 W/mm
0E
2F
r in
.
1
10
1-4
15 1
1 -2
-10 10
10
10
103
Time [sec]
Figure 3-9. Dynamic RON transients after OFF (VGSQ= -10 V, VDSQ= 50 V) to ON switching
event for samples subjected to HP-state stress under different conditions. The red solid line
indicates a very large increase of dynamic RON up to five-fold RON-DC at 200 ns only after 3 min HP
stress at VDS= 30 V (P= 9 W/mm). In comparison with the RON/RONDC increase after 20 min HP
stress at lower VDS of 20 V and higher P level of 12 W/mm in pink dashed line, this result suggests
that HP stress at higher VDS promotes greater dynamic RON degradation. In all cases, a very fast
RON recovery down to the ms range is observed.
64
Through the HP-stress test, GaN HEMTs experience not only very high temperature in the
channel region but also a high electric field which can potentially produce copious amounts of hot
electrons [10]. These can create the damage that is behind the observed degradation of dynamic RON. The
roles of
VDS
and temperature in the degradation of dynamic RON during HP stress can be separated by
performing tests at different bias conditions.
In Figure 3-9, we show the evolution of dynamic RON normalized to its DC value after an HPstress experiment at a higher VDS of 30 V but lower power level around 9 W/mm (by reducing the DC
stress current). The channel temperature is expected to be lowered down to 291 'C. Even after only 3 min
of this HP stress, the dynamic RON at 200 ns in response to an OFF to ON switching event (same
conditions as earlier in this chapter) increases five-fold over the DC value, as shown in Figure 3-9. When
compared with the much smaller
RON/RONDC
increase after 20 min of HP stress at a lower VDS of 20 V
and higher power level around 12 W/mm (also shown in the graph), this result suggests that HP stress at
higher VDS induces greater dynamic
RON
degradation. Under these new conditions, the
RON
transients
show fast recovery in the sub-ms range suggesting the same physical origin of the created traps in both
experiments.
Our recent studies of dynamic RON in AlGaN/GaN high-voltage HEMTs (the section 2.4) suggest
that epitaxial growth conditions greatly matter [5]. Here, we illustrate how different growth protocols of
otherwise identical structures also yield markedly different robustness of dynamic
RON
to high power
electrical stress. For this purpose, we have tested devices made from wafers grown by a different epi
supplier (denoted here as "epi supplier II" in contrast with the results presented up to now in this chapter
on samples from a different "epi supplier I"). They are identical to the ones studied in the section 2.3 of
the previous chapter. The two wafers were processed into devices in the same lot. Figure 3-10 shows the
time evolution of normalized DC RON and lDMAX as well as IGOFF during a constant HP-stress experiment
65
on a device from a wafer grown by epi-supplier II. The stress conditions are identical to those of Figure 32 (VGs= 2 V and VDS= 20 V), but the stress period is lengthened to 2 hr. In spite of this longer stress time,
in the epi-supplier II sample, in contrast to the epi-supplier I case, negligible degradation is observed in
RON and IDMAX during this stress test. A large increase of
JIGOFF
is observed but we find this to be fully
recoverable under sufficient visible-light illumination.
Epi-supplier 11
1.2
100
0DMAX
10
ON
E
E
-.90.6
z
GOFF
- I*.1
1
E
LA.
0
_0
0.4
0.1
0
0.2
0
0.01
0
20
40
60
80
100
120
Time [min]
Figure 3-10. Time evolution of normalized DC RON, IDMAX and IIGOFF in a constant HP-state
stress in devices made from a different epi-supplier sample (denoted as epi-supplier II). The stress
conditions are those of Figure 3-2 (VGs= 2 V, VDS= 20 V) but the stress time is extended to 2 hr. In
the epi-supplier II sample, there is no prominent permanent degradation in RON, IDMAX and |IGOFFI.
The large increase of IIGOFF is fully recoverable under sufficient illumination of visible light.
Dynamic RON transients after identical OFF
(VGSQ=
-10 V, VDsQ= 50 V) to ON switching events
were also measured before and after 2 hr HP-stress test in the epi-supplier II sample and are shown in
Figure 3-11. Compared with the intrinsic dynamic
RON
transient characteristic of the virgin epi-supplier
II sample, there is only a minor increase in the dynamic RON observed even after the 2 hr HP stress. This
66
is also much less than the dynamic
RON
transient observed in the sample from epi-supplier I after much
shorter stress under the same conditions. This result suggests that epi-supplier II devices are more robust
to HP-state stress than those of epi-supplier I. A detailed study of the origin of this is beyond the scope of
our research goal in this chapter. However, two possible explanations are apparent. The different buffer
design in the two structures affects the thermal conductance of the substrate. In fact, the thermal
resistance of the device from epi-supplier II is estimated to be lower than 10 'C/W which is one third of
that of the equivalent epi-supplier I sample. A much lower channel temperature during the same HP stress
should be less harmful to the device. In addition, the epi-supplier II sample has a greater concentration of
long-time constant traps than the epi-supplier I sample [5]. When these traps held electrons, they alleviate
the electric field profile inside the device [11]. For the same VDs bias condition, a device structure with a
greater concentration of traps might then be more robust to hot-electron induced degradation.
12
1
OFF(-10 V, 50 V) to ON
10 min HP-stress
S840
A~e'
0
0
-
on Epi-supplier I
6
S 4
2 hr HP-stress
onEpi-supplier 11
2
Virgin Epi-supplier II
10-6 10--5 104-4 10--3 102-2
1 0-1 1 10 0 11
Time [sec]
1 022 1033
Figure 3-11. Dynamic RON transient after an OFF (VGSQ= -10 V, VDsQ= 50 V) to ON
switching event on epi-supplier Il sample before and after 2 hr HP stress at VGS= 2 V and VDS= 20
V (P~- 12 W/mm). In contrast to the large degradation of dynamic RON in epi-supplier I device after
the 40 min HP-stress (purple dashed line), there is only a minor increase of dynamic RON observed
after 2 hr HP stress in epi-supplier 11 sample.
67
3.4.
Conclusions
We have experimentally observed a large increase in dynamic RON on a short-time scale after
high-power electrical stress of GaN HEMTs. The cause is attributed to the formation of shallow traps
inside the AlGaN barrier or at its surface. A rich spectrum of traps with different binding energies has
been identified. This work suggests that prolonged device operation of GaN HEMTs under RF power
conditions (in microwave applications) or under hard-switching conditions (in power management) can
result in an undesirable increase of dynamic RON on a very short time scale.
3.5.
References
[1] G. Meneghesso, F. Rampazzo, P. Kordos, G. Verzellesi, and E. Zanoni, "Current Collapse and HighElectric-Field Reliability of Unpassivated GaN/AlGaN/GaN HEMTs," IEEE Trans. Electron Devices,
vol. 53, no. 12, pp. 2932-2941, Dec. 2006.
[2] J. A. del Alamo and J. Joh, "GaN HEMT reliability," Microelectron. Reliab., vol. 49, no. 9-11, pp.
1200-1206, Sep. 2009.
[3] D. Jin and J. A. del Alamo, "Methodology for the Study of Dynamic ON-Resistance in High-Voltage
GaN Field-Effect Transistors," IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3190-3196, Oct.
2013.
[4] J. Joh and J. A. del Alamo, "A Current-Transient Methodology for Trap Analysis for GaN High
Electron Mobility Transistors," IEEE Trans. Electron Devices, vol. 58, no. 1, pp. 132-140, Jan. 2011.
[5] D. Jin and J. A. del Alamo, "Mechanisms responsible for dynamic ON-resistance in GaN highvoltage HEMTs," in 2012 24th InternationalSymposium on Power Semiconductor Devices and ICs
(ISPSD), 2012, pp. 333-336.
[6] S. A. Vitusevich, 0. A. Antoniuk, M. V. Petrychuk, S. V. Danylyuk, A. M. Kurakin, A. E. Belyaev,
and N. Klein, "Low-frequency noise in AlGaN/GaN HEMT structures with AlN thin film layer,"
Phys. Status Solidi C, vol. 3, no. 6, pp. 2329-2332, 2006.
[7] D. M. Fleetwood, M. R. Shaneyfelt, and J. R. Schwank, "Estimating oxide El trap, interface E trap, and
border~ltrap charge densities in metal E oxidel semiconductor transistors," Appl. Phys. Lett., vol. 64,
no. 15, pp. 1965-1967, Apr. 1994.
[8] A. R. Arehart, A. Sasikumar, G. D. Via, B. Winningham, B. Poling, E. Heller, and S. A. Ringel,
"Spatially-discriminating trap characterization methods for HEMTs and their application to RFstressed AlGaN/GaN HEMTs," in Electron Devices Meeting (IEDM), 2010 IEEE International,2010,
pp. 20.1.1-20.1.4.
[9] A. Sozza, C. Dua, E. Morvan, M. A. diForte-Poisson, S. Delage, F. Rampazzo, A. Tazzoli, F.
Danesin, G. Meneghesso, E. Zanoni, A. Curutchet, N. Malbert, N. Labat, B. Grimbert, and J.-C. De
Jaeger, "Evidence of traps creation in GaN/AlGaN/GaN HEMTs after a 3000 hour on-state and off-
68
state hot-electron stress," in Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE
International,2005, p. 4 pp.-593.
[10]M. Meneghini, A. Stocco, R. Silvestri, N. Ronchi, G. Meneghesso, and E. Zanoni, "Impact of hot
electrons on the reliability of AlGaN/GaN High Electron Mobility Transistors," in Reliability Physics
Symposium (IRPS), 2012 IEEE International,2012, pp. 2C.2.1-2C.2.5.
[11] S. Demirtas and J. A. del Alamo, "Effect of trapping on the critical voltage for degradation in GaN
high electron mobility transistors," in Reliability Physics Symposium (IRPS), 2010 IEEE
International,2010, pp. 134-138.
69
70
Chapter 4. Total current collapse in high-voltage GaN-on-Si
MIS-HEMT
4.1.
Introduction
In the previous chapters, we have investigated dynamic RON or current collapse characteristics
and their degradation as a result of high power stress in high voltage GaN-on-SiC HEMTs in great detail.
The devices studied before were designed for high-voltage RF power amplifier application. In this chapter,
GaN power switching devices are studied with the purpose of investigating the current collapse
phenomenon in the high voltage OFF-state condition up to around 1000 V. In order to achieve this goal, a
new experimental set up has been established to handle both very high voltage and accurate
characterization in a user-safe environment. In addition, a research collaboration with Texas Instruments
has been established with the goal of achieving fundamental understanding of current collapse
phenomenon in industrially prototyped GaN Metal-Insulator-Semiconductor
High-Electron-Mobility
Transistors (MIS-HEMTs) fabricated on large-diameter Si substrates.
GaN MIS-HEMT power transistors have emerged as promising candidate components for future
high-voltage power management applications. The gate dielectric in MIS structures can reduce OFF-state
leakage current significantly compared to the Schottky gate structure widely used in RF power amplifier
71
applications. In addition, GaN-on-Si epitaxial wafer technology guarantees substantial cost benefits in the
fabrication process, as discussed in chapter 1. However, in order for this device to become commerciallyviable, current collapse or dynamic RON phenomenon should be investigated and mitigated to the greatest
extent. To suppress this effect along with enhancing the voltage handling ability of these devices, multi
field-plate structures are utilized [1]. While valuable in this regard, their effectiveness to prevent current
collapse is unclear, particularly at high voltage [2]. Our goal here is to study this important issue in depth.
In this work, we have investigated current collapse in GaN MIS-HEMTs with multiple fieldplates designed for > 600 V operation. In the OFF-state, when VDS exceeds around 200 V, we observe
trapping that is so severe that leads to total current collapse and the device effectively behaves as an
"open" when subsequently biased in the ON state. This phenomenon is fully recoverable and repeatable.
The impact of device geometry and temperature on this anomaly has been investigated and the
responsible activation energies for the trapping/detrapping dynamics have been extracted. All of our
experimental results are consistent with electron trapping inside the AlGaN barrier or the GaN channel
that takes place through a tunneling process under high-electric-field. We term this "Zener trapping". The
understanding from our work suggests that current collapse can be mitigated through careful attention to
defect control during epitaxial growth of GaN-on-Si wafer and appropriate design of the field plate
structure of the device.
72
4.2.
Experimental set up
Figure 4-1. Diagram of power device characterization set-up built in the lab. DC and AC
stress/characterization can be carried out by Agilent B1505A and Auriga pulsed IV on the Cascade
Tesla high-power probe station. Pulsed UV light source system is developed to test detrapping effect
depending on light illumination with different wavelength. Automatic computer control
environment for each instrument has been developed as well. High voltage test functionality up to
3000V is established from the entire set-up.
In order to obtain thorough understanding of these issues on GaN high voltage power transistors,
we have built a unique reliability test set up which is briefly illustrated in Figure 4-1. At the center of this
set up is a Cascade Tesla high power probe station which can handle voltages up to 10,000 V. This probe
station incorporates a safety laser light curtain which can immediately shut down any on-going high
voltage measurements inside the probe station if a breach of the laser curtain is detected. Our system also
includes
an Agilent B1505A power device analyzer which can perform very accurate device
characterization in the voltage range up to 3000 V. In addition, our Auriga pulsed IV system has been
upgraded to allow a higher voltage range up to 600 V. In addition to these instruments, a pulsed UV light
illumination system has been designed and built to test accelerated detrapping in devices through light
illumination.
73
Xenon fiber optic light source
-250nm (5.0 eV) - 1100nm (1.1 eV)
UV light illuminationsystem
A?
Computer-controlled monochromator
- Tunable
bandpass filters for light
Automated filter wheel
-A
six position wheel controls intensity
of light source
On the probe station
UV optical fiber
-
Draw the output of light source to
the probed device
Figure 4-2. Pulsed UV light source system consisting of Xenon fiber optic light source,
computer controllable monochromator, and automated filter wheel. The brief functional
description per each one is scripted. The UV optical fiber tip drawing the output of light source
system is placed closely to the sample on the probe station, as shown on the right, so as to beam UV
light directly onto the top of the sample.
Figure 4-2 illustrates the details of our pulsed UV light source system. It consists of a Xenon fiber
optic light source which generates a wide light spectrum from 250 nm up to 1100 nm wavelength. A
computer controllable monochromator has been attached to the output of the light source. This is a
tunable bandpass filter through which we can select any preferred light wavelength. In addition to the
controllability of wavelength, an automated filter wheel has been attached to control the intensity of the
filtered light. This is a six-position wheel and each position can hold a specific filter with different
degrees of transparency. These positions can be selected by means of computer control. Lastly, one end of
the UV optical fiber is connected to the final output of the automated filter wheel and the other end is
74
located very close to the device under test on the probe station such that the output of the light source
shines directly onto the probed device. Since any UV light leakage from this system can be very
detrimental to the user, the system is enclosed in a UV safety box made by polycarbonate plates which are
also covered with a UV filter film. This safety box encloses the Xenon fiber light source and the rest of
optical system, as shown in the right of Figure 4-1. All of these parameters of UV light source system can
be controlled by the same main computer machine which controls all the other measurement instruments
such as pulsed IV and power device analyzer.
4.3.
Total current collapse under OFF-state stress
IDun (VGS= 0
(b)
(a)
V,
VDS=
0.2 V)
VDS
FP3
FP1
FP2
0.2V
OFF-state stress
characterization
VGS
GaN
V
-
VT -5V
10 s at every step
Figure 4-3 (a) Three field plate structures (FP1, FP2, and FP3) placed in a stairway fashion
along the gate-to-drain gap in AlGaN/GaN MIS-HEMTs. (b) The waveform of VDs and VGS in the
OFF-state step-stress experiment. VDS continually steps up while VGS is biased at VT - 5 V. Every
stress period is 10 s. Between each step, IDun which is defined at VGS= 0 V, VDS= 0.2 V is periodically
monitored. IDfln is inversely proportional to
RON.
75
The devices studied here are industrially prototyped AlGaN/GaN MIS-HEMTs fabricated on a 6inch Si wafer. They feature three field plates placed in a stairway fashion along the gate-to-drain gap as
shown in the Figure 4-3 (a). The breakdown voltage is > 600 V and RON and IDMAX are 10 Q-mm and 550
mA/mm, respectively.
To study the impact of high-V stress on
RON,
we perform OFF-state step-stress experiments. In
these experiments, we gradually step VDSSTRESS while constantly biasing VGs at VT - 5 V. The continuous
waveform of VDS and VGS in the OFF-state step-stress is illustrated in the Figure 4-3 (b). Between each
step-stress, we periodically perform fast measurements of the linear drain current
(IDun,
defined at VGS= 0
V, VDS= 0.2 V) which is inversely proportional to RON as well as the transfer and output characteristics.
1
VGS= VT-
0.8
5
V
0.6
0.4
0.2
RON/RON(O) >1 010
0
0
200
400
VDSSTRESS
600
(V)
800
Figure 4-4. Evolution of normalized IDn in an OFF-state step-stress experiment. VGS is
biased at VT - 5 V and VDS is step-stressed by 20 V every 10 seconds up to 720 V. Total current
collapse occurs for VDSSTRESS> 3 0 0 V and RON increases by -10 orders of magnitude at the end of the
experiment.
76
Figure 4-4 shows the evolution of normalized IDun in a typical experiment in which VDS increases
by 20 V every 10 seconds up to 720 V. We find that up to
VDSSTRESS=
200 V, IDun degrades slightly, about
10%. Around 200 V, IDun abruptly drops to around 10% of its initial value. For higher VDSSTRESS, IDun
continues to degrade and eventually when VDS > 300 V, total current collapse occurs. At the end of
experiment,
RON
increases correspondingly by -10
orders of magnitude! This behavior has been
consistently observed in devices across the 6-inch wafer. This total current collapse phenomenon is a
significant concern to AlGaN/GaN MIS-HEMT power-switching technology and demands urgent
attention.
From this experimental observation to the total current collapse phenomenon, our work aims to
answer several key aspects. First of all, we want to understand the recoverability of this phenomenon and
evaluate any permanent degradation that might be taking place. Trapping and non-trapping related effects
need to be distinguished. Secondly, the location of this phenomenon inside the device needs to be
identified. In addition, the dynamics of this process should be understood and the physical mechanism
responsible for this should be identified. Lastly, ways to mitigate or eliminate this problem should be
suggested based on our best understanding.
4.4.
Recovery of total current collapse
In order to comprehend the recovery of this total current collapse phenomenon, we have
performed consecutive OFF-state step-stress experiments on the same sample. Each experiment is
followed by a detrapping step in which we illuminate strong UV light and apply a thermal treatment at
200'C for at least 180 min to the sample. Strikingly, the fully degraded IDlin shows complete recovery
after each detrapping step and in the next run of OFF-state step-stress experiment, completely identical
characteristics of total current collapse are replicated. Figure 4-5 shows this full recovery characteristic
clearly during 6 consecutive experiments on the same device. These experiments are fully repeatable
77
without inducing any permanent degradation in the device. This suggests that there is neither trap creation
nor any kind of permanent damage as a result of these current collapse experiments.
1
OFF-state stre ss:
VGS =VT- 5
0.8
0
3
1st run
V
rd
4th
~0.4
6th
0.2
0
0
100
300
200
VDSSTRESS
400
(V)
Figure 4-5. Six consecutive OFF-state step-stress experiments up to 400 V on the same
sample. Detrapping procedure with UV exposer and thermal treatment (180 min at 200*C) has
been applied in between each run. Total current collapse characteristic shows complete recovery
and repeatability after detrapping procedures suggesting that this results from completely trapping.
4.5. Extension and location of current blockage
In order to understand this serious problem, we have carried out detailed characterization of the
devices in their collapsed state. Figure 4-6 shows the output characteristics before and after 300 sec of
OFF-state stress at 300 V. After high-voltage stress, we observe nearly complete current collapse at low
VDS.
However, for higher VDS, the drain current starts flowing again. This behavior is characteristic of
channel punch-through [3], [4] suggesting that the blockage region where trapping takes place is
relatively short along the channel direction. Since the lateral extent of current blockage region is very
short, any current cannot flow through the channel region at low
VDS
but as VDS increases, a small amount
of current eventually can pass through this region depending on the VDS value, as shown in Figure 4-6
78
(right). This result indicates that the excessive trapping occurs in a highly localized region inside the
device.
600
After STRESS
14
Vs-VT=_7 V
Virgin
5
V
12
500
E%
E 400 -IE
300
E
E 200
100
5V
IE
#
'E
3V
After 300 VI
STRESS
-
#
1 V
VGS-V= 7 V
10
1v
8
6
4
~2 2
-1V
0
0
3
6
9
12
15
0
3
6
12
9
15
VDS (V)
VDS (V)
Figure 4-6. Output characteristics before (blue) and after (red) 300 sec of OFF-state stress
at VDS STRESS= 300 V and VGS= VT - 5 V. After stress, at low VDS, nearly complete current collapse is
observed. However, as VDs increases the drain current starts flowing again. The collapsed output
characteristics resemble a punchthrough device.
1.E+02
VDS=
Virgin
0.2
V
1.E+00 E
,
I~
300 V
II~J
360 V
------------..
V-O
E
E
100 V
1.E-04
400 V
1.E-06
500 V
-2
0
2
4
6
VGS-VTO (V)
Figure 4-7. Evolution of the linear subthreshold characteristics (VDs= 0.25 V) during the
stress of Figure 4-3. VTO is the initial threshold voltage where ID is 1 pA/mm. VT does not change at
all under total current collapse.
79
Additionally, we have investigated the evolution of the subthreshold characteristics (Figure 4-7)
during the stress of Figure 4-4 in a semi-log scale as a function of Vcs
-
VTO where VTO is the initial
threshold voltage. Here, threshold voltage is defined at ID= 1 uA-mm. First of all, during on-state where
VGS-VT0 > 0 V, as VDS stress becomes higher than 200 V, on-state current drops significantly with
VDSSTRESS
eventually down to the noise level. This is consistent with our observation of IDun degradation
in Figure 4-4. However, interestingly, in the subthreshold regime, this figure shows that VT is unaffected
at all from this effect. This result suggests that the channel current blockage responsible for current
collapse is not located underneath the gate as this would induce a large shift in VT. Instead, the excessive
trapping occurs in the extrinsic region of the device.
1.E+02
1.E+01
E 1.E+00
S 1.E-01
C,)
- S1.
E-02
1.E-04
0
200
100
VDSSTRESS
300
400
(V)
Figure 4-8. Evolution of source (Is), gate (IG), drain (ID), and substrate (IB) currents during
the stress periods of Figure 4-5 up to 400 V. As the OFF-state bias increases beyond 300 V, the
drain-to-substrate current increases. At the onset of severe trapping, all currents are negligible.
80
Figure 4-8 shows the evolution of the 4 terminal currents during the stress of Figure 4-4. As the
stress voltage increases beyond 300 V, the drain-to-substrate current becomes dominant. However, at the
onset of severe trapping, all currents are rather negligible, less than 1 nA/mm. This result may suggest
that the onset of excessive trapping is weakly related to the evolution of the terminal currents and has a
different origin.
1
. longer
1
LGD
0.8
standard
S0.
C .6
0.4
0.8
S
short
~long
short
0.4
0.2
0
0
0
200
100
300
VDS STRESS
400
0.8
(V)
.-0.6
0
0
100
300
200
VDSSTRESS
()
short
0.4
0.2
400
(d)
400
long
0.6
0.2
0
300
(V)
LFp3
0.8
CD
short
200
VDSSTRESS
0-
long
_
100
1
LFP2
standard
0
(b)
1
(c)
standard
0.6
long
0.2
(a)
LFPl
standard
0
100
200
300
400
VDSSTRESS (V)
Figure 4-9. Impact of device geometry on IDun degradation under OFF-state step-stress up to
VDs-sTREss= 400 V and VGS= VT - 5 V. The trapping characteristics do not depend on gate-to-drain
gap length (LGD), Vs field plate length (LFP1), 2 d field plate length (LFP2) and 3 rd field plate length
(LFP3).
81
It is now clear that the trapping responsible for total current collapse takes place in the extrinsic
region of the device. To pinpoint its location with greater precision, we have examined the impact of
device geometry between gate and drain electrodes where the high field extends at high voltage. We have
performed identical OFF-state step stress up to 400 V on devices with different geometries of the gate-todrain gap
(LGD),
field plate
the 1t field plate length (Lm1 ), the 2 "d field plate length (Lm), and the P
3
length (Lm). As shown in the Figure 4-9, any device geometry variation along the channel direction does
not affect the trapping characteristics in a significant way. This result strongly suggests that the total
current collapse phenomenon must correlate with the evolution of electric-field peak because this is
expected to be relevant for trapping and also relatively independent of any variation of device geometry
along the channel direction. Any difference in the vertical distance from the field plates down to the
channel can change the evolution of the electric field and presumably the total current collapse
characteristic as well. We do not have devices that allow us to explore this dependency.
FP1
1
0.8
8
00.6
VGS= VT - 5 V
FP2
FP2
FP2
FP3
FP1
FP3
j0.4
0.2
GaN
0
0
100
200
VDs (V)
300
400
Figure 4-10. Normalized drain-to-gate capacitance (CDG) in the OFF state as a function of
The three steps in CG indicate the complete extension of the depletion region under each of
the three field plates by VDs= 50 V. For VDS> 50 V, electric field peaks in the channel under the
edge of FP3 and where VDS is around 200 V, excessive trapping occurs along this highly localized
region and can form very short current blockage region under the edge of FP3 as shown in the
cartoon on the right.
VDs.
82
In order to understand the evolution of the electrostatics of the device at high voltage in the OFF
state, we, have investigated capacitance-voltage characteristics of a virgin device. Figure 4-10 graphs the
drain-to-gate capacitance in the OFF state as a function of
VDS.
The three steps that are observed indicate
sequential extension of the depletion region under each of the three field plates. We can conclude the
complete channel depletion under FP3 occurs around VDS= 50 V. Hence, for voltages beyond VDS= 50 V,
the electric field in the channel peaks under the edge of the third field-plate and increases with voltage.
Around VDS= 200 V where we observe the onset of current collapse, the electric field peak can become so
high that it can trigger a rapid trapping mechanism. Then, we postulate that it is at this precise location,
under the outer edge of the third field-plate, where the blockage to the channel current is induced as
shown in the cartoon on the right of Figure 4-10.
4.6.
Trapping and detrapping dynamics
To gain a greater insight of this phenomenon, we have investigated trapping and detrapping
dynamics in more details. First, we have performed OFF-state step-stress at different temperatures from
25 to 200 'C on the same device. In Figure 4-11 (a), we show that the trapping behavior is rather
insensitive to temperature up to 200 'C. In addition, the evolution of the four terminal currents over this
entire temperature range in Figure 4-11 (b) indicates that substantial increase of them does not impact on
this phenomenon at all. This confirms again that they are not the main source of electron trapping. The
temperature insensitivity of the phenomenon suggests that trapping takes place through a tunneling
process.
83
1
0.9
0.8
0 0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2000C
100
(a)
E
E
E
CD
'D
E
250C
/S
'A
0
(b)
0C
00 00
100
200
0C
100
00
2500C
200
VDSSTRESS
300
300
200
VDSSTRESS
200
5V
250C
0
1.E+00
1.E-01
1.E-02
1.E-03
1.E-04
1 .E-05
1 .E-06
1.E+00
1.E-01
1.E-02
1.E-03
1.E-04
1 .E-05
1 .E-06
VGS= VT-
1 0
E
400
(
1.E+00
1.E-01
1.E-02
1.E-03
1.E-04
1.E-05
1.E-06
1.E+00
1.E-01
1.E-02
1.E-03
1 .E-04
1.E-05
1.E-06
40C
200
00
25 C
0
(V)
0C
100
200
VDSSTRESS
300
400
(V)
Figure 4-11. (a) Evolution of IDn, in OFF-state step-stress experiment at temperatures from
25 to 200 'C. The trapping characteristics are insensitive to temperature. (b) Evolution of drain (ID),
source (Is), gate (IG), and substrate (IB) currents at different temperatures. The terminal currents
are not the main source of electron trapping.
84
Zener tunneling law:
(b)
(a)
1
VGS= VT
EPEAK
0.8
0
In(T) = A (E -E)K/2 + B
5V
1000
0.6
- ----- --- ------ --
0.4
0
4)
1401V
0.2
(I)
160 V
1
100
10
ET-Ev= 1 eV
18
0
2
6
4
Time (min)
8
10
1
0.3
0.32 0.34 0.36
1/EPEAK (cm/MV)
Figure 4-12. (a) Evolution of normalized IDn as a function of time in a device under
constant stress bias from VDS_STRESS=140 to 180 V at room temperature. A characteristic trapping
time (r) is defined at the 50% degradation point of 'DIin. (b) Zener dependence of c: t vs. I/EPEAK in a
semi-log scale. EPEAK is the peak value of electric field inside AlGaN layer under FP3 estimated from
field simulations in the same OFF-state bias conditions (Figure 4-13). The straight line that is
obtained strongly suggests a Zener tunneling process. A trap energy level of around 1 eV above
valence band edge is estimated.
To probe this, we study the dynamics of trapping. Figure 4-12 (a) shows the time evolution of
normalized IDun under constant stress at different voltages. IDun degradation greatly speeds up with voltage.
We define a characteristic trapping time r at 50% degradation of IDin- In Figure 4-10 (b) we plot T vs.
I/EPEAK where EPEAK is the peak value of electric field inside the AlGaN barrier layer under the edge of
FP3 estimated from field simulations by Silvaco (described below). This is the characteristic Zener
tunneling law [5]. The excellent linearity that is obtained strongly suggests a valence-band-to-trap
tunneling process. We call this "Zener trapping." If we use the following equation for Zener trapping
ln(T) =
1
3
4(2m )2(ET - EV)2
85
+ B
where Mh*is a hole effective mass (the average hole mass value around 1.0(±0.5) mo is used [6]), and B is
a constant, a trap energy level of around 1 eV above the valence band edge is estimated from the Zener
tunneling law.
To gain greater insight into this problem, we have also studied the recovery dynamics of fully
trapped devices. At room temperature in the dark, the complete recovery can take many days. The
recovery process can be accelerated at higher temperatures as shown in Figure 4-13 which shows IDun
recovery transients after 600 sec OFF-state stress at
VDS=
200 V at different temperatures from 140 'C to
200 'C. Increasing temperature clearly accelerates the recovery. We extract the dominant recovery time
constant [7] and find that it has an activation energy of around 0.63 eV (Figure 4-13, right).
The recovery is also accelerated under UV light illumination. Figure 4-14 shows the UV lightinduced recovery transients at room temperature of a device collapsed after 3 min at VDs= 300 V. During
the recovery period, no external bias is applied to the collapsed device but we illuminate it with UV light
of different wavelengths that are selected by a monochromator out of a broadband light source. Without
any light, the recovery of the fully collapsed IDn is negligible in the entire recovery period but the
enhanced recovery behavior is observed as light energies become higher than 2.8 eV. This result may
indicate that the trap energy levels responsible for total current collapse are located under the conduction
band by about 2.8 eV.
86
18.5
1
18
0 0.8
0
C
C
0.6
0.4
-
e17.5
200*C
i55*C
1700C
0.2
0-
100
2
102
101
t (sec)
---
103
EA
= 0.63 eV
16.5
140*C
in
10~1
b17
16
10
24
26
28
30
1/kT (eV')
Figure 4-13. Normalized IDi recovery transients in the dark after 600 sec OFF-state stress
at VDSSTRESS= 200 V and VGS= VT - 5 V at different temperatures. IDInDC is the virgin DC value of
IDin. As T increases, the recovery speeds up. An activation energy of around 0.63 eV is extracted.
Recovery
Stress!
1
0.8
0
4.1 eV
0.6
3.1 eV
0.4
0.2
2.8 eV
0
0
10
5
15 Dark 20
Time (min)
Figure 4-14. UV-induced recovery of a device collapsed after 300 V OFF-state stress for 3
min for different energies of UV light at room temperature. Enhanced recovery is observed for
light energies above 2.8 eV.
87
4.7. Electric field simulation
(a)
(b)
7
E
7
EPEAK
6
5
5
00.
Wi
2
0
3
W2
1000 V
00 V
03
100
I
Gate FP1
FP2
4
U
FP3
0
Space
200 400 600 8001000
VDS (V)
Figure 4-15. (a) Evolution of electric field at the top surface of AlGaN barrier from gate to
drain obtained from TCAD simulations (Silvaco). Beyond VDs= 2 0 0 V, the peak electric field
appears under the edge of the outermost field plate and increases with VDS. (b) Magnitude of EPEAK
under third field-plate edge vs. VDS is described. At VDS= 200 V, EPEAK is around 3.4 MV/cm and it
increases up to 6.4 MV/cm at 1,000 V.
In order to estimate the evolution of electric field profile in the OFF-state condition, we have
performed electric field simulation by using TCAD simulation tool of Silvaco. In Silvaco, we construct
fine mesh-grid structure of GaN MIS-HEMTs design with three field plates placed in gate-to-drain gap. In
electrostatic condition, the 2DEG charge inside AlGaN/GaN heterostructure has been generated through
the formation of spontaneous and piezoelectric sheet charge calculated from AlGaN and GaN material
model given by Silvaco. The density value of 2DEG in this electrostatic condition has been adjusted to fit
to the experimental measurement of 2DEG value by appropriately scaling the entire polarization charge
density in the AlGaN/GaN heterostructure. The location of multi-field plate structures in the simulation
structure has been determined to induce the sequential extension of channel depletion in the OFF-state
condition identically to the one observed in Figure 4-10. Based on these setting, the electric field profile
88
inside GaN MIS-HEMTs structure in the OFF-state condition up to 1000 V has been simulated through
Silvaco.
Figure 4-15 (a) shows the evolution of electric field profile at the top surface of AlGaN barrier
layer from gate to drain at different OFF-state bias conditions. In this field simulation, we can confirm
that increasing VDs beyond the voltage that depletes the 2DEG under the outer-most field plate results in a
sharply peaked electric field distribution with the peak located right under the third field plate edge.
Figure 4-15 (b) shows that the magnitude of
simulations indicate that at
VDS=
EPEAK
under the edge of FP3 increases with VDS. Our
200 V just inside the AlGaN surface,
increases to 6.4 MV/cm at 1,000 V. These results indicate that
EPEAK
EPEAK can
is around 3.4 MV/cm and it
approach to significantly high
values in our multi-field plate design of GaN MIS-HEMTs in the OFF-state condition of several hundred
volts. In this case, if there are unoccupied trap region near the valence band which are a reservoir of
electrons, then this high electric field can possibly trigger electron tunneling process from the valence
band to the trap sites.
4.8. Mechanism for total current collapse
All the observations reported here are consistent with a field-induced trapping process that takes
place right under the edge of the outer-most field plate at high enough OFF-state voltage. As shown in the
field simulation of Figure 4-15, under the edge of the outer most field plate close to the semiconductor
surface, we can conclude that the electric field can be so intense that direct tunneling of electrons from the
valence band to trap levels in the AlGaN barrier or the GaN channel can take place (Figure 4-16). This
type of tunneling process is consistent with our temperature insensitive observations and the absence of
geometrical dependencies. We want to call this "Zener trapping". After high voltage is released and the
device is biased in ON-state, the trapped electrons lift the conduction band up and create a highly
localized current blockage region under the edge of FP3 as shown in Figure 4-17.
89
AIGaN barrier
GaN channel
Zener
trapping
~
~
EYB
Figure 4-16. Proposed Zener trapping mechanism responsible for the observed total current
collapse. Direct electron tunneling from the valence band into defect states can be triggered under
intense electric-field inside the AlGaN barrier layer or at the top of the GaN channel.
FP1
FP2
FP3
GaN
thermal
detrapping
E
EYB
EV
I'
_--T
-e
"
Figure 4-17. Energy band diagram along surface from gate to drain with device biased in
the linear regime after a total current collapse event. OFF-state trapping results in a sharp energy
barrier directly below the edge of the outermost field plate that blocks current. In the linear regime,
thermal detrapping can take place as indicated with an activation energy substantially lower than
the ionization energy of the trap.
90
The energy location of the traps that are responsible for total current collapse can be assessed
from our experimental measurements. From the Zener tunneling law calculation, we estimate a trap
energy level about 1 eV above the valence band edge. From UV detrapping experiments, a trap energy
located around 2.8 eV below the conduction band edge appears responsible. The combination of these
energy levels matches very well the bandgap of 3.8 eV for Al 0.2Ga0 .8N and quite closely that of 3.4 eV for
GaN. Figure 4-18 shows the estimated trap energy level located inside the band structure.
Ec
Ehv= 2.8 eV
EYB -- =~
tE
::
E_
V
T-EV= 1.0 eV
Figure 4-18. Energy location of traps responsible for Zener trapping. From Zener trapping
calculations, ET - Ev = 1.0 eV is extracted and from UV detrapping experiments, Eh, = 2.8 eV is
estimated.
The much lower activation energy of 0.63 eV observed in the thermal detrapping process in
Figure 4-13 seems to be inconsistent with the estimated energy picture in Figure 4-18. However, this
could be explained from the sharply localized nature of the trapping which might allow thermal trap-toconduction band transitions at significantly lower energies, as illustrated in Figure 4-17.
Our hypothesis suggests that a similar phenomenon should also occur on the source side of the
device if the bias is reversed. Indeed this has been observed. In VDS=O V step-stress experiments, total
current collapse also occurs but at a reduced voltage, as shown in Figure 4-19. This is due to the absence
of field-plate structure that smooths out the electric field. As on the drain side, this degradation is fully
recoverable after UV illumination and high temperature baking though with a reduced activation energy
91
of 0.50 eV. This is understandable since the trapping location in this case is right next to the gate where in
the linear regime the electron concentration is high.
1
16
15
14
13
%#1MO
12
11
0.8
00.6
EA= 0.50 eV
CM4
0.4
-0.2
0
0
12
24
36
25
48
IVGSSTRESSI (V)
27 29 31
1/kT (eV-1)
33
Figure 4-19. Evolution of IDn under VDs=O V condition as VGS steps from -12 V to -48 V
with 1 V/step every 30 sec at room temperature. Sharp current collapse is observed as well. In this
case, the channel blockage occurs under the source end of the gate. Thermal acceleration behavior
in this source-side recovery is clearly observed with an activation energy of 0.50 eV, as shown on
the right.
The traps involved in the total current collapse process are likely to be those responsible for
yellow luminescence in AlGaN and GaN. They are reported to be located at a depth from the conduction
band of around 2.5 eV in GaN [8] and 2.8 eV in A10 .2 Gak.8 N [9]. The energy picture of Figure 4-18 from
our UV light detrapping experiments (Figure 4-14) and our estimate from the Zener law (Figure 4-12b)
are rather consistent with yellow luminescence report in A10.2Ga 0.8N but could possibly also work for GaN
given the uncertainty in all measurements and analysis. Recent studies attribute yellow luminescence to
substitutional C in the N site [10] though other hypotheses have been formulated [11]-[13]. C is a
common dopant in high-voltage GaN FET heterostructures. Our work proposes that the possible existence
of C impurity inside the GaN heterostructures might be the physical origin causing this total current
collapse phenomenon through Zener trapping process.
92
4.9. Conclusions
In summary, we report total current collapse in high-voltage GaN MIS-HEMTs induced by Zener
trapping at high voltage. The current collapse is fully recoverable and repeatable. The traps are consistent
with those responsible for yellow luminescence in GaN and AlGaN. We suspect carbon impurity as the
trap responsible for the observed total current collapse. The understanding derived here suggests that this
effect can be mitigated through attention to defect control during epitaxial growth and appropriate design
of the field plate structure of the device.
4.10. References
[1] R. Chu, A. Corrion, M. Chen, R. Li, D. Wong, D. Zehnder, B. Hughes, and K. Boutros, "1200-V
Normally Off GaN-on-Si Field-Effect Transistors With Low Dynamic on -Resistance," IEEE
Electron Device Lett., vol. 32, no. 5, pp. 632-634, 2011.
[2] W. Saito, Y. Kakiuchi, T. Nitta, Y. Saito, T. Noda, H. Fujimoto, A. Yoshioka, T. Ohno, and M.
Yamaguchi, "Field-Plate Structure Dependence of Current Collapse Phenomena in High-Voltage
GaN-HEMTs," IEEE Electron Device Lett., vol. 31, no. 7, pp. 659-661, Jul. 2010.
[3] J. J. Barnes, K. Shimohigashi, and R. W. Dutton, "Short-channel MOSFET's in the punchthrough
current mode," IEEE Trans. Electron Devices, vol. 26, no. 4, pp. 446-453, Apr. 1979.
[4] J. Zhu, R. A. Martin, and J. Y. Chen, "Punchthrough current for submicrometer MOSFETs in CMOS
VLSI," IEEE Trans. Electron Devices, vol. 35, no. 2, pp. 145-151, Feb. 1988.
[5] J. G. Fossum, A. Ortiz-Conde, H. Shichijo, and S. K. Baneijee, "Anomalous leakage current in
LPCVD PolySilicon MOSFET's," IEEE Trans. Electron Devices, vol. 32, no. 9, pp. 1878-1884, Sep.
1985.
[6] M. Suzuki, T. Uenoyama, and A. Yanase, "First-principles calculations of effective-mass parameters
of AlN and GaN," Phys. Rev. B, vol. 52, no. 11, pp. 8132-8139, Sep. 1995.
[7] J. Joh and J. A. del Alamo, "A Current-Transient Methodology for Trap Analysis for GaN High
Electron Mobility Transistors," IEEE Trans. Electron Devices, vol. 58, no. 1, pp. 132-140, Jan. 2011.
[8] E. Calleja, F. J. Sanchez, D. Basak, M. A. Sainchez-Garcia, E. Munioz, I. Izpura, F. Calle, J. M. G.
Tijero, J. L. Sinchez-Rojas, B. Beaumont, P. Lorenzini, and P. Gibart, "Yellow luminescence and
related deep states in undoped GaN," Phys. Rev. B, vol. 55, no. 7, pp. 4689-4694, Feb. 1997.
[9] D. R. Hang, C. H. Chen, Y. F. Chen, H.-X. Jiang, and J. Y. Lin, "AlxGal-xN/GaN band offsets
determined by deep-level emission," J.Appl. Phys., vol. 90, no. 4, pp. 1887-1890, Aug. 2001.
[10]J. L. Lyons, A. Janotti, and C. G. V. de Walle, "Carbon impurities and the yellow luminescence in
GaN," Appl. Phys. Lett., vol. 97, no. 15, p. 152108, Oct. 2010.
[1 1]J. Neugebauer and C. G. V. de Walle, "Gallium vacancies and the yellow luminescence in GaN,"
Appl. Phys. Lett., vol. 69, no. 4, pp. 503-505, Jul. 1996.
[12]A. Sedhain, J. Li, J. Y. Lin, and H. X. Jiang, "Nature of deep center emissions in GaN," Appl. Phys.
Lett., vol. 96, no. 15, p. 151902, Apr. 2010.
93
[13]R. Armitage, W. Hong, Q. Yang, H. Feick, J. Gebauer, E. R. Weber, S. Hautakangas, and K. Saarinen,
"Contributions from gallium vacancies and carbon-related defects to the 'yellow luminescence' in
GaN," Appl. Phys. Lett., vol. 82, no. 20, pp. 3457-3459, May 2003.
94
Chapter 5. Summary and suggestions
5.1.
Summary
In this thesis, we have investigated the dynamic ON-resistance (RON) phenomenon in high voltage
GaN Field-Effect-Transistors. This consists of a substantial increase of
RON
after an OFF-to-ON
switching operation that takes a certain period of time to recover. This phenomenon can greatly degrade
the efficiency of electrical power management circuits that adopt GaN power transistor technology and is
seen as a critical huddle preventing the wide deployment of this technology. We investigate this important
physical behavior in depth in this thesis.
To broaden the fundamental understanding of this important phenomenon, we have developed a
new dynamic
RON
transient measurement methodology which allows the observation of
RON
transients
after a switching event over a time period that starts around 200 ns and can span many decades. The
usefulness of this technique has been demonstrated through a systematic study of dynamic RON on highvoltage GaN HEMTs on SiC substrate as a function of time, temperature and pulse conditions. We find
that dynamic
RON
transient characteristics become much worse as the OFF-state switching voltage
increases. Two distinct mechanisms have been identified with different time scales and temperature
95
behavior. First, there are dynamic recovery transients on a short time scale that are temperature
independent. In contrast, there are also dynamic
RON
transients with long time constants displaying a
thermally activated behavior. We attribute the fast recovery transients to electron detrapping through a
tunneling process from traps inside the AlGaN barrier close to the GaN channel. Interface states at the
AlN spacer/AlGaN barrier interface are the main suspects. The slower thermally-activated recovery takes
place from traps in the AlGaN or at the surface. Moreover, after a High-Power to ON switching, only fast
detrapping through a temperature independent process is observed. This is also consistent with trapping at
the AlGaN/AlN interface. These findings provide a path to engineer a GaN power-switching transistor
with minimum dynamic RON problems.
To advance our understanding of dynamic
RON
characteristics in high-voltage GaN-on-SiC
HEMTS using our new technique, we have explored the degradation of dynamic RON characteristics as a
result of electrical stress. Especially, the impact of high-power stress on dynamic
RON
is investigated. Our
methodology clearly indicates that the accumulated stress from high power state operation which occurs
frequently in RF power amplifier operation or during hard-switching operation can significantly degrade
the dynamic RON characteristics in the sub-ms range. This occurs as a result of the stress-induced creation
of traps with relatively short time constants. On a longer time scale, negligible degradation of dynamic
RON
iS observed. The cause is attributed to the formation of shallow traps inside the AlGaN barrier or at
its surface. A rich spectrum of traps with different binding energies has been identified. This work
suggests that prolonged device operation of GaN HEMTs under RF power conditions (in microwave
applications) or under hard-switching conditions (in power management) can result in an undesirable
increase of dynamic RON on a very short time scale. Our results highlight the importance of characterizing
electrically stress-induced dynamic RON and current collapse over very short time scales.
This thesis has also advanced the understanding of current collapse phenomenon in high voltage
GaN power switching transistors up to around 1000 V of OFF-state bias condition. To achieve this goal,
96
new experimental test set up as well as a new research collaboration with Texas Instruments has been
established. Fundamental understanding of current collapse phenomenon in industrially prototyped GaN
MIS-HEMTs fabricated on large-diameter Si substrates has been pursued. In particular, the effectiveness
of multi field-plate structures to prevent current collapse is evaluated in depth. From our work, in the
OFF-state when VDs exceeds around 200 V, we observe very intensive trapping leading to total current
collapse which effectively makes the device as an "open" when subsequently biased in the ON state. This
total current collapse is fully recoverable and repeatable. We have carried extensive experimental studies
of this phenomenon, including temperature dependence, trapping and detrapping dynamics and
dependence on the geometry of the device. All of our experimental results suggests electron trapping
inside the AlGaN barrier or the GaN channel that takes place through a tunneling process under highelectric-field. We term this "Zener trapping". The traps are consistent with those responsible for yellow
luminescence in GaN and AlGaN. We suspect carbon impurity as the trap responsible for the observed
total current collapse. The understanding from our work suggests that current collapse can potentially be
mitigated through careful attention to defect control and appropriate design of the field plate structure of
the device.
5.2.
Suggestions for mitigating dynamic ON-resistance phenomenon
Our systematic studies of the dynamic
RON
characteristics in GaN transistors suggest several
directions to explore in order to mitigate this phenomenon. First of all, our findings from chapter 2 show
that there are at least two different families of traps in a GaN heterostructure. One family consists of
conventional traps probably located at the surface or inside the AlGaN barrier layer [1], [2]. These can be
minimized through continuous optimization of epitaxial growth techniques. In addition to this, electron
trapping into these defect sites or surface donor states generating 2 DEG [3] must be also minimized. This
mostly comes from the adjacent gate electrode through gate-to-drain leakage currents in the high-voltage
97
OFF-state condition. Therefore these trapping effects can be greatly reduced if appropriate gate dielectrics
and surface passivation films are utilized to develop novel MIS (Metal-Insulator-Semiconductor)
structures [4], [5]. The main purpose is to prevent electrons from being injected into any trap site or
surface donor states in the high voltage OFF-state condition which induces current collapse [6], [7].
The other origin of trap sites postulated in our work is the potential existence of interface traps in
the GaN cap/AlGaN barrier/AlN spacer layer heterostructure. The addition of AlN spacer layer in the
standard AlGaN/GaN structure to increase device performance such as electron mobility and 2 DEG
density [8]-[1 1] may introduce poor current collapse through interface states [12], [13]. The quality of the
interface either at the AlN spacer/GaN channel layer or at the AlGaN barrier/AlN spacer layer must be
thoroughly evaluated to guarantee good reliability and current collapse characteristics. Otherwise, if there
is a substantial amount of interface states behaving as border traps near the channel, then these can be
occupied with electrons overflowing from the channel. This can easily happen especially in the high drain
current density case such as the high power state condition. In this condition, large amount of electrons
accelerated by the high drain bias turn into hot carriers which can overcome the potential barrier and get
trapped in these interface traps. Therefore, the need for the insertion of an AIN space layer right above the
channel needs to be carefully examined. One suggestion to evaluate this issue is to perform thorough
comparison studies between GaN devices without AIN spacer layer and identical ones with AlN space
layer grown by the same vendor. In order to clearly evaluate the impact of the AlN layer while excluding
any effect from the fabrication process, both structures are necessary to be processed in the same lot. The
series of systematic studies performed in our thesis is a good way to evaluate this issue in detail. The use
of different epi-growth vendors definitely can also affect this issue and careful selection of proper vendor
is an important consideration as well.
Our studies of the impact of high power stress on dynamic RON in chapter 3 also indicate several
important aspects which should be considered to mitigate dynamic RON issues. We showed that prolonged
98
operation in the high power state can generate many trap sites which dramatically increase dynamic
RON
characteristics. More rigorous systematic studies of this kind must be performed in the future. Three
different aspects determining high power state such as current density, bias voltage, and temperature
should be adequately separated. Our preliminary results in chapter 3 show that hot carriers might be the
most important factor degrading the dynamic RON characteristics through trap generation. Therefore, the
electric field profile must be carefully managed to minimize carrier acceleration. The electric field profile
can be optimized through a better structure of field plates or adding more field plates [14]-[16]. A better
thermal design to reduce channel temperature in the high power state operation is also very important as
suggested in our work. The thermal dissipation capability can be greatly enhanced through different
device layout, packaging and buffer structures [17]-[20].
Our investigation on high voltage GaN-on-Si MIS-HEMTs in chapter 4 draws an important
conclusion that multi-field plates need to be optimized to handle very high voltage appropriately. In our
case, a triple field plate structure fully depletes the channel after applying a VDs as low as about 50 V in
the OFF-state. This is relatively small compared with the maximum blocking voltage in excess of 600 V.
The thickness of the passivation layer underneath the field plates needs to be increased to smooth out the
electric field profile under high voltage conditions. This should be able to suppress the peak value of the
electric field along the edge of the field plates over the current design. An additional field plate may be
necessary as well. In addition, our total current collapse phenomenon indicates the existence of trap sites
that induce intense electron trapping at high voltage. Our studies suggest that C impurity might be the
physical reason. Other studies indicate that Fe as well as C can be a source of current collapse from buffer
traps [21]. Therefore, the elimination of problematic impurities above the buffer layers is very important
to mitigate dynamic RON. The top active region of the AlGaN/GaN heterostructure, in particular, must be
free from any impurities as much as possible. This may include any structural defects or dislocations [22],
[23] which can potentially impact dynamic RON as well. All of these presented issues should be carefully
considered in the engineering of GaN-on-Si epitaxial growth.
99
5.3.
Suggestions for future research
Though intensive investigation of dynamic RON in high-voltage GaN FETs has been performed in
our thesis, we would like to suggest several important areas which require advanced studies especially in
GaN MIS-HEMTs structures as below.
First, hot carrier related degradation phenomena are big concerns that require more thorough
understanding. This degradation can involve charge trapping issues into the surface, barrier and/or buffer
regions resulting in current collapse [24]. Hot carriers can also induce defect generation [25]. In order to
understand this effect clearly, GaN MIS-HEMTs should have minor current collapse in the OFF-state
condition up to their designed operational voltage. Large amount of current collapse in the OFF-state as
observed in our studied devices can easily mask other important degradation mechanisms. Therefore,
target devices should first be developed to have minimum current collapse or other reliability issues in the
OFF-state. After this has been confirmed, thorough investigation about hot carrier effects through
different combination of drain current levels and drain-to-source voltage must be performed. Channel
temperature is another important parameter in the analysis of hot carrier effects and developing a new
way to measure this during the operation in the high power state condition is another important research
that needs to be performed.
Secondly, current collapse in GaN MIS-HEMTs may include some response from interface states
at the top surface layer or inside the GaN heterostructure. To study this, capacitance-voltage (C-V)
measurements constitute an effective tool to understand this issue quantitatively [26]. Adopting C-V
measurements in our systematic stress and characterization measurement routine will be very powerful to
provide another vision along with other measurements of figure of merits. Different frequency
measurements at different temperatures or under UV illumination with light of different wavelengths can
also be worthy of in depth exploration. C-V characteristics as a function of electrical stress in multi-field
100
plate structures can also be an interesting area to investigate. Hot carrier effects discussed above can also
be explored in more depth through the analysis of C-V characteristics.
Thirdly, analysis of current collapse characteristics under high frequency pulsed operation is also
an important area to explore. All of our studies on GaN MIS-HEMTs are based on DC stress and
characterization. However, since these devices are designed to operate at high frequency up to possibly
several MHz, the characterization of dynamic RON under AC operation condition is an important new area
to investigate. The evolution of dynamic
RON
depending on the operational frequency at different
operational voltage can be investigated first. Our pulsed IV system with a 600 V pulser will be the ideal
tool to explore this area. The impact of soft-switching and hard-switching condition on dynamic RON as
well as other device and switching parameters can be also studied using this system. Hot carrier effects
under pulsed AC conditions can be investigated as well. The development of a customized computer
control environment for this pulsed IV system will be necessary in order to obtain large amount of data
efficiently during long periods of testing time.
Finally, appropriate life time models should be developed for GaN MIS-HEMTs technology that
accounts for the understanding of physical degradation behavior such as current collapse or other relevant
ones. New life time models will be determined by observing dominant degradation mechanisms in future
GaN power switching device technologies. This will be essential to assess the qualification of this
technology. Proper theoretical modeling consistent with experimental measurements will form the core of
these life time models.
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101
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