CMS ENDCAP MUON VME 9U TRIGGER MOTHERBOARD
Preliminary User’s Manual
Rice University
06/24/1999
CMS Endcap Muon 9U Trigger Motherboard (TMB) Prototype receives LCT data from
one Cathode LCT card (CLCT) and one Anode LCT card (ALCT) [1]. The main
functions of the TMB are:
-
-
synchronization of the incoming anode and cathode data to its local clock
alignment of the anode and cathode tags by their Bunch Crossing Numbers (because
Anode LCT data arrives several clock earlier then the Cathode LCT data)
correlation of the Anode and Cathode LCT words and construction of the two
combined “Muon LCT”
communication with Muon Port Card (MPC) and DAQ Motherboard (DAQMB)
1. Interface to Clock and Control Board (CCB)
TMB receives four signals from CCB via twisted pair flat cable. Pin assignment of the
20-pin header (3M 2520-5002UB, Digikey Part Number MHD20K-ND) is given in
Table 1.
Contact
1
3
5
7
9
11
13
15
17
19
Signal
GND
CLOCK+
GND
BX0+
GND
RESET+
GND
L1ACC+
GND
GND
Contact
2
4
6
8
10
12
14
16
18
20
Table 1
Signal
GND
CLOCKGND
BX0GND
RESETGND
L1ACCGND
GND
TMB uses Reset signal to set its internal BXN and L1ACC counters into predefined (by
CSR2 bits) state. BX0 signal enables BXN counter to count on the next (BX1) clock
cycle and enables L1ACC counter to count on the next L1ACC signal.
2. Interface to LCT99 modules
TMB receives anode and cathode LCTs from two LCT99 [1] anode and cathode
modules. Pin assignment of the 50-pin connector for communication with LCT99 cards
is given in Table 2. Data formats for Anode and Cathode LCTs are given in Tables 3 and
4 respectively.
Table 2
Contact
Signal
Contact
Signal
1
GND
2
GND
3
RxOUT0+ (1)
4
RxOUT0- (1)
5
GND
6
GND
7
RxOUT1+ (1)
8
RxOUT1- (1)
9
GND
10
GND
11
RxOUT2+ (1)
12
RxOUT2- (1)
13
GND
14
GND
15
RxCLK+ (1)
16
RxCLK- (1)
17
GND
18
GND
19
RxOUT3+ (1)
20
RxOUT3- (1)
21
GND
22
GND
23
RxOUT0+ (2)
24
RxOUT0- (2)
25
GND
26
GND
27
RxOUT1+ (2)
28
RxOUT1- (2)
29
GND
30
GND
31
RxOUT2+ (2)
32
RxOUT2- (2)
33
GND
34
GND
35
RxCLK+ (2)
36
RxCLK- (2)
37
GND
38
GND
39
RxCLK3+ (2)
40
RxOUT3- (2)
41
GND
42
GND
43
GND
44
GND
45
GND
46
GND
47
GND
48
GND
49
GND
50
GND
(1) corresponds to Channel Link 1 (1st best LCT), and (2) corresponds to Channel Link
2 (2nd best LCT)
Table 3
Anode LCT Data Format
Bit
Bit ID
Bit Description
0
AVALIDbn
Anode Valid Pattern Flag: 1=Valid Pattern, 0=No Valid Pattern
1
APATbn0
Pattern Quality 0-3: Implies # of hits
2
APATbn1
Pattern Quality 0-3: Implies # of bits
3
ACCMUbn
Accelerator Muon Flag: 1=Parallel Pattern, 0=Normal Pattern
4
WGbn0
Wire GANG ID Number 0-111
5
6
7
8
9
10
11
12
13
14
15
16-27
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23-27
WGbn1
WGbn2
WGbn3
WGbn4
WGbn5
WGbn6
ABXNbn0
ABXNbn1
ABXNbn2
ABXNbn3
ABXNbn4
AREXbn0-11
Bit ID
CVALIDbn
CPATbn0
CPATbn1
CPATbn2
CPATbn3
CPATbn4
CPATbn5
CPATbn6
CPATbn7
BENDbn
HSbn0
HSbn1
HSbn2
HSbn3
HSbn4
HSbn5
HSbn6
HSbn7
CBXNbn0
CBXNbn1
CBXNbn2
CBXNbn3
CBXNbn4
RES0-4
Bunch Crossing Number 0-31
Reserved
Table 4
Cathode LCT Data Format
Bit Description
Cathode Valid Pattern Flag: 1=Valid Pattern, 0=No Valid Pattern
Pattern ID 0-255: Inplies priority, bend angle, position, # of hits
Bend Direction: 0=Left, 1=Right
½-Strip ID Number 0-159
Bunch Crossing Number 0-31
Cathode Bunch Crossing ID Number 0-31
Reserved
3. Anode/Cathode Matching Logic and Status Bits
16 combinations of four input anode and cathode Flags are possible (Table 5).
Table 5
A1 Flag
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A2 Flag
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C1 Flag
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C2 Flag
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Comment
No incoming LCTs
One ALCT, no CLCT
One ALCT, no CLCT
Two ALCT, no CLCT
One CLCT, no ALCT
One ALCT and one CLCT
One ALCT and one CLCT
Two ALCT and one CLCT
One CLCT, no ALCT
One ALCT and one CLCT
One ALCT and one CLCT
Two ALCT and one CLCT
Two CLCT and no ALCT
Two CLCT and one ALCT
Two CLCT and one ALCT
Two ALCT and two CLCT
Two status bits STA[1..2] inform Global Muon Trigger about possible combinations of
Anode and Cathode LCTs (Table 6).
Table 6
STA1 STA2
Comment
0
0
No CSC trigger data (all anode and cathode Flags=0) (line 1 in Table 5)
1
0
Ambiguous LCTs (lines 2, 3, 4, 5, 7, 9, 10, 11, 12, 13, 15 in Table 5)
0
1
2 ALCT + 1 CLCT or 1 ALCT + 2 CLCT (lines 8, 14 in Table 5)
1
1
One or two unambiguous muons (lines 6 and 16 in Table 5)
Anode preprocessing inside the ALCT card is faster than cathode preprocessing inside
the CLCT card, and because of this the incoming anode and cathode LCT are not aligned
in time. TMB contains input pipeline logic in order to delay anode LCT for up to 10
cycles (this number is programmable, CSR1) and align the anode and cathode LCT by
their BXN on the output of the TMB.
In the case of only one Anode LCT and one Cathode LCT, the LCTs are matched
according to Bunch Crossing Number (BXN). The Anode LCT has more precise BXN,
and it is taken to be the BXN of the muon. The Cathode LCT BXN can differ by +/-1
bunch crossing. For each of the selected muons TMB outputs two Bunch Crossing Match
Bits, BXMA<1..2> (related to first best muon), and BXMB<1..2> (related to second best
muon). All possible combinations are listed in Table 7.
Table 7
BXM<1>
0
1
0
1
BXM<2>
0
0
1
1
Comment
ABXN-CBXN=0
ABXN-CBXN=1
ABXN-CBXN=-1
I ABXN-CBXN I > 1
If two muons happen to hit the same wire-gang, but different strips, the TMB will receive
2 Anode and 1 (first best) Cathode LCT. The TMB outputs 2 Muon LCTs, by copying
the Cathode LCT bits into both muons. The case of 2 Cathode LCTs and 1 Anode LCT is
handled in a similar fashion.
If there are two unambiguous LCTs (2 ALCT + 2 CLCT) in one chamber, they are
matched according to their pattern magnitudes (largest ALCT and largest CLCT, second
largest ALCT and second largest CLCT).
It is also possible that the TMB receives 1 or 2 CLCTs and 0 ALCTs, and vice-versa. In
each case, there is nothing to match, but TMB still outputs the non-zero LCT data, and
zeroes for the missing LCT.
4. Interface to MPC
All signals transmitted from TMB to MPC are listed in Table 8.
Signals
Valid Pattern Flag
Cathode Pattern Number
Cathode Bend Angle (Right/Left)
Cathode ½-Strip ID
Anode Pattern Quality
Accelerator Muon
Anode Wire-Gang ID
Anode Bunch Crossing Number
LCT1 BX Matching Bits BXMA<1..2> (Related to Muon1)
LCT2 BX Matching Bits BXMB<1..2> (Related to Muon2)
TMB Status Bits STA1<1..2> (Related to CSC Trigger)
TMB Status Bits STB2<1..2> (Related to CSC/RPC Trigger)
Sync Error
Reserved
Total
* These bits =0 for the current TMB prototype
** Common bits for two muons
Table 8
Number of bits
1 * 2 LCT
8 * 2 LCT
1 * 2 LCT
8 * 2 LCT
2 * 2 LCT
1 * 2 LCT
7 * 2 LCT
5 (**)
2
2
2 (**)
2 (*) (**)
1 (**)
4
84
These bits are transmitted to MPC via three National DS90CR285/286 Channel Links.
Each of these links converts 28 bits of data into four data streams and one clock streams.
List of signals and pin assignment are given in Tables 9 and 10 respectively. 64-pin highdensity connectors (Circuit Assembly Header CA-64NFHR, Socket CA-64NFS-12G or
similar) are used.
Table 9
Channel LCT
Signal
Channel LCT
Signal
Channel LCT
Signal
Link1
Link2
Link3
Bit_0
1
FLAG
Bit_0
1
W_BX1
Bit_0
2
S_HS5
Bit_1
1
S_PAT1
Bit_1
1
W_BX2
Bit_1
2
S_HS6
Bit_2
1
S_PAT2
Bit_2
1
W_BX3
Bit_2
2
S_HS7
Bit_3
1
S_PAT3
Bit_3
1
W_BX4
Bit_3
2
S_HS8
Bit_4
1
S_PAT4
Bit_4
1
W_BX5
Bit_4
2
W_PQ1
Bit_5
1
S_PAT5
Bit_5
1
BXMA1
Bit_5
2
W_PQ2
Bit_6
1
S_PAT6
Bit_6
1
BXMA2
Bit_6
2
W_AMU
Bit_7
1
S_PAT7
Bit_7
1
STA1
Bit_7
2
W_GID1
Bit_8
1
S_TAP8
Bit_8
1
STA2
Bit_8
2
W_GID2
Bit_9
1
S_L/R
Bit_9
1
STB1
Bit_9
2
W_GID3
Bit_10
1
S_HS1
Bit_10
1
STB2
Bit_10
2
W_GID4
Bit_11
1
S_HS2
Bit_11
1
SYER
Bit_11
2
W_GID5
Bit_12
1
S_HS3
Bit_12
1
Bit_12
2
W_GID6
Bit_13
1
S_HS4
Bit_13
1
Bit_13
2
W_GID7
Bit_14
1
S_HS5
Bit_14
2
FLAG
Bit_14
2
W_BX1
Bit_15
1
S_HS6
Bit_15
2
S_PAT1 Bit_15
2
W_BX2
Bit_16
1
S_HS7
Bit_16
2
S_PAT2 Bit_16
2
W_BX3
Bit_17
1
S_HS8
Bit_17
2
S_PAT3 Bit_17
2
W_BX4
Bit_18
1
W_PQ1
Bit_18
2
S_PAT4 Bit_18
2
W_BX5
Bit_19
1
W_PQ2
Bit_19
2
S_PAT5 Bit_19
2
BXMB1
Bit_20
1
W_AMU Bit_20
2
S_PAT6 Bit_20
2
BXMB2
Bit_21
1
W_GID1 Bit_21
2
S_PAT7 Bit_21
2
STA1
Bit_22
1
W_GID2 Bit_22
2
S_PAT8 Bit_22
2
STA2
Bit_23
1
W_GID3 Bit_23
2
S_L/R
Bit_23
2
STB1
Bit_24
1
W_GID4 Bit_24
2
S_HS1
Bit_24
2
STB2
Bit_25
1
W_GID5 Bit_25
2
S_HS2
Bit_25
2
SYER
Bit_26
1
W_GID6 Bit_26
2
S_HS3
Bit_26
2
Bit_27
1
W_GID7 Bit_27
2
S_HS4
Bit_27
2
FLAG – Valid Pattern Flag
S_PAT<1.8> - Strip Pattern Number
S_L/R – Strip Left/Right Bend
S_HS<1..8> - Half-Strip ID
W_PQ<1..2> - Anode Pattern Quality
W_AMU – Accelerator Muon
W_GID<1..7> - Anode Wire-Gang ID
W_BX<1..5> - Anode Bunch Crossing Number
BXM<1..2> - Anode/Cathode Bunch Crossing Matching Status Bits
STA<1..2> - CSC Trigger Status Bits
STB<1..2> - CSC/RPC Trigger Status Bits (always “0” for current TMB prototype)
SYER – Synchronization Error
Table 10
Pin Channel
TMB
MPC
Pin Channel
TMB
MPC
Link
Signal
Signal
Link
Signal
Signal
1
GND
GND
2
GND
GND
3
1
TxOUT0+
RxIN0+
4
1
TxOUT0RxIN05
GND
GND
6
GND
GND
7
1
TxOUT1+
RxIN1+
8
1
TxOUT1RxIN19
GND
GND
10
GND
GND
11
1
TxOUT2+
RxIN2+
12
1
TxOUT2RxIN213
GND
GND
14
GND
GND
15
1
TxCLK+
RxCLK+
16
1
TxCLKRxCLK17
GND
GND
18
GND
GND
19
1
TxOUT3+
TxIN3+
20
1
TxOUT3RxIN321
GND
GND
22
GND
GND
23
2
TxOUT0+
RxIN0+
24
2
TxOUT0RxIN025
GND
GND
26
GND
GND
27
2
TxOUT1+
RxIN1+
28
2
TxOUT1RxIN129
GND
GND
30
GND
GND
31
2
TxOUT2+
RxIN2+
32
2
TxOUT2RxIN233
GND
GND
34
GND
GND
35
2
TxCLK+
RxCLK+
36
2
TxCLKRxCLK137
GND
GND
38
GND
GND
39
2
TxOUT3+
RxIN3+
40
2
TxOUT3RxIn341
GND
GND
42
GND
GND
43
3
TxOUT0+
RxIN0+
44
3
TxOUT0RxIN045
GND
46
GND
GND
GND
47
3
TxOUT1+
RxIN2+
48
3
TxOUT1RxIN149
GND
GND
50
GND
GND
51
3
TxOUT2+
RxIN2+
52
3
TxOUT2RxIN253
GND
GND
54
GND
GND
55
3
TxCLK+
RxCLK+
56
3
TxCLKRxCLK57
GND
GND
58
GND
GND
59
3
TxOUT3+
RxIN3+
60
3
TxOUT3RxIN361
GND
GND
62
GND
GND
63
GND
GND
64
GND
GND
5. Interface to DAQMB
TMB sends selected LCT bits to DAQMB using National Channel Link DS90CR285
transmitter. Pin assignment of the 26-pin connector and data format are given in Tables
11 and 12 respectively.
Contact
1
3
5
7
9
11
13
15
17
19
21
23
25
Bit
1
2-3
Signal
GND
TxOUT0+
GND
TxOUT1+
GND
TxOUT2+
GND
TxCLK+
GND
TxOUT3+ (1)
GND
GND
GND
Contact
2
4
6
8
10
12
14
16
18
20
22
24
26
TMB – DAQMB Data Format
Function
Flag (=1 when valid data word is transmitted)
Bit2 (BXMA1) Bit3(BXMA2) (Related
0
0
1
0
0
1
1
1
Table 11
Signal
GND
TxOUT0GND
TxOUT1GND
TxOUT2GND
TxCLKGND
TxOUT3GND
GND
GND
Table 12
to 1st best LCT)
ABXN-CBXN=0
ABXN-CBXN=1
ABXN-CBXN=-1
I ABXN-CBXN I > 1
4-5
Bit4 (BXMB1) Bit5 (BXMB2) (Related to 2nd best LCT)
0
0
ABXN-CBXN=0
1
0
ABXN-CBXN=1
0
1
ABXN-CBXN=-1
1
1
I ABXN-CBXN I > 1
6-7
Bit6 (STA1) Bit7 (STA2)
0
0
No CSC Trigger Data
1
0
Ambiguous LCTs
0
1
2CLCT+1ALCT or 1CLCT+2ALCT tags
1
1
One or two unambiguous LCTs
8
9-13
14-16
17-28
SyncError (=1 in case of mismatched ABXN and internal BX counter)
Anode BXN
L1ACC counter
Not used, always “0”
TMB sends a data word to DAQMB upon getting L1ACC from CCB. If L1ACC doesn’t
arrive within 128 clock cycles (3.2 us) after INTTRIG (in case of internal triggering)
signal, this data is dumped.
6. Control and Status Registers
TMB consists of two 16-bit Control and Status Registers (CSR) (Tables 13 and 14).
Table 13
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CSR1
Meaning
Reserved
Source of trigger to generate L1ACC (*)
Source of trigger to generate L1ACC (*)
Triggering scheme (**)
Triggering scheme (**)
Delay of the Anode LCT from ALCT (***), LSB
Delay of the Anode LCT from ALCT (***), MSB
Delay of the Anode LCT from ALCT (***), MSB
Delay of the Anode LCT from ALCT (***), HSB
Enable/Disable ACQUIRE Mode (=1: Enable, =0: Disable) (****)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
*
Bit_1 Bit_2
0
0 External Trigger (from LEMO EXT connector on the front panel)
1
0 Reserved
0
1 Internal Trigger (from TMB internal logic, based on LCT data)
1
1 VME Command
**
Bit_3 Bit_4
0
0 Coincidence of Anode and Cathode LCT
1
0 Anode LCT only
0
1 Cathode LCT only
1
1 Anode LCT or Cathode LCT
Upon getting of either external or internal trigger (according to CSR1<1..4>) TMB
transmits anode and cathode patterns to MPC and generates 100 ns INT pulse on the
front panel.
*** 1..10 clock periods in respect to Cathode LCT
**** When ACQUIRE mode is enabled, TMB generates trigger signal to CCB only
once upon receiving LCT valid trigger after external ACQUIRE pulse. If ACQUIRE
mode is disabled, TMB generates trigger signal to CCB on every incoming valid LCT
pattern (Internal Triggering) or External Trigger (External Triggering).
Table 14
CSR2
Bit
Meaning
0
Internal BXN Counter, LSB
1
Internal BXN Counter
2
Internal BXN Counter
3
Internal BXN Counter
4
Internal BXN Counter, HSB
5
Reserved
6
Reserved
7
L1ACC Counter, LSB
8
L1ACC Counter, MSB
9
L1ACC Counter, HSB
10
Reserved
11
Reserved
12
Reserved
13
Reserved
14
Reserved
15
Reserved
7. Test Registers
There are eight test registers (four inside Anode PLD and four inside Cathode PLD).
Data from test registers can substitute data words from LCT boards and can be used for
testing of the TMB internal logic. Data format for anode and cathode test registers are
given in Tables 15 and 16 respectively.
Table 15
Bit
1
2
3
4
5
6
7
8
9
10
11
12
13
Test Register 1
ALCT1<0>
ALCT1<1>
ALCT1<2>
ALCT1<3>
ALCT1<4>
ALCT1<5>
ALCT1<6>
ALCT1<7>
ALCT1<8>
ALCT1<9>
ALCT1<10>
ALCT1<11>
ALCT1<12>
Anode Test Registers 1..4
Test Register 2
Test Register 3
ALCT1<16>
ALCT2<0>
ALCT1<17>
ALCT2<1>
ALCT1<18>
ALCT2<2>
ALCT1<19>
ALCT2<3>
ALCT1<20>
ALCT2<4>
ALCT1<21>
ALCT2<5>
ALCT1<22>
ALCT2<6>
ALCT1<23>
ALCT2<7>
ALCT1<24>
ALCT2<8>
ALCT1<25>
ALCT2<9>
ALCT1<26>
ALCT2<10>
ALCT1<27>
ALCT2<11>
ALCT2<12>
Test Register 4
ALCT2<16>
ALCT2<17>
ALCT2<18>
ALCT2<19>
ALCT2<20>
ALCT2<21>
ALCT2<22>
ALCT2<23>
ALCT2<24>
ALCT2<25>
ALCT2<26>
ALCT2<27>
-
14
15
16
ALCT1<13>
ALCT1<14>
ALCT1<15>
-
ALCT2<13>
ALCT2<14>
ALCT2<15>
Table 16
Bit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Test Register 1
CLCT1<0>
CLCT1<1>
CLCT1<2>
CLCT1<3>
CLCT1<4>
CLCT1<5>
CLCT1<6>
CLCT1<7>
CLCT1<8>
CLCT1<9>
CLCT1<10>
CLCT1<11>
CLCT1<12>
CLCT1<13>
CLCT1<14>
CLCT1<15>
Cathode Test Registers 1..4
Test Register 2
Test Register 3
CLCT1<16>
CLCT2<0>
CLCT1<17>
CLCT2<1>
CLCT1<18>
CLCT2<2>
CLCT1<19>
CLCT2<3>
CLCT1<20>
CLCT2<4>
CLCT1<21>
CLCT2<5>
CLCT1<22>
CLCT2<6>
CLCT1<23>
CLCT2<7>
CLCT1<24>
CLCT2<8>
CLCT1<25>
CLCT2<9>
CLCT1<26>
CLCT2<10>
CLCT1<27>
CLCT2<11>
CLCT2<12>
CLCT2<13>
CLCT2<14>
CLCT2<15>
Test Register 4
CLCT2<16>
CLCT2<17>
CLCT2<18>
CLCT2<19>
CLCT2<20>
CLCT2<21>
CLCT2<22>
CLCT2<23>
CLCT2<24>
CLCT2<25>
CLCT2<26>
CLCT2<27>
-
For testing procedure the desired data words should be written into Test Registers 1..8
and then “Run Test” VME Write Command (see Table 17) should be generated. Bits
CSR1<5..7> during this test should be set to “0”.
8. VME Interface
TMB performs A24D16 VME Slave Function. Base Address is selectable using DIP
Switches S6 (bits A8…A15) and S7 (bits A16..A23). If switch is in “On” state, the bit is
“0”. If switch is in “Off” state, the bit is “1”. During TMB initial testing and debugging
base address D00000(hex) is used. Decoded addresses and VME commands are listed
in Table 17.
Table 17
Address (hex)
Access
Register
Base + 0
Read/Write
Test Register 1 (inside Anode PLD)
Base + 2
Read/Write
Test Register 2 (inside Anode PLD)
Base + 4
Read/Write
Test Register 3 (inside Anode PLD)
Base + 6
Read/Write
Test Register 4 (inside Anode PLD)
Base + 8
Read/Write
Test Register 5 (inside Cathode PLD)
Base + a
Read/Write
Test Register 6 (inside Cathode PLD)
Base + c
Read/Write
Test Register 7 (inside Cathode PLD)
Base + e
Read/Write
Test Register 8 (inside Cathode PLD)
Base + 10
Read/Write
CSR1 (inside Control PLD)
Base + 12
Base + 14
Read/Write
Read
Base + 16
Base + 18
Base + 1a
Base + 1c
Base + 1e
Base + 20
Base + 22
Base + 24
Base + 26
Base + 28
Base + 2a
Base + 2c
Base + 2e
Base + 30
Write
Write
Write
Write
Read
Read
Read
Read
Read
Read
Read
Read
Read
CSR2 (inside Control PLD)
FIFO Status Register (inside both Anode and Cathode
PLD)
Set Internal Trigger INTTRG signal
Reset TMB internal logic
Reserved
Reset both Anode and Cathode FIFO buffers
Run Test
Anode FIFO1 (inside Anode PLD)
Anode FIFO2 (inside Anode PLD)
Anode FIFO3 (inside Anode PLD)
Anode FIFO4 (inside Anode PLD)
Cathode FIFO1 (inside Cathode PLD)
Cathode FIFO2 (inside Cathode PLD)
Cathode FIFO3 (inside Cathode PLD)
Cathode FIFO4 (inside Cathode PLD)
Reserved
9. FIFO Buffers
TMB accumulates selected LCTs in its internal FIFO memory available for reading via
VME. The depth of the FIFO is 8 words. Data format is given in Tables 18 and 19. FIFO
status (Empty and Full Flags) also available via VME from FIFO Status Register (Table
20).
Table 18
Anode FIFO Buffers
Bit
FIFO1
FIFO2
FIFO3
FIFO4
0
LCT1_FLAG
LCT1_AREXBN0
LCT2_FLAG
LCT2_AREXBN0
1 LCT1_APATBN0
LCT1_AREXBN1
LCT2_APATBN0
LCT2_AREXBN1
2
LCT1_APATBN1
LCT1_AREXBN2
LCT2_APATBN1
LCT2_AREXBN2
3 LCT1_ACCMUBN LCT1_AREXBN3 LCT2_ACCMUBN LCT2_AREXBN3
4
LCT1_WGBN0
LCT1_AREXBN4
LCT2_WGBN0
LCT2_AREXBN4
5
LCT1_WGBN1
LCT1_AREXBN5
LCT2_WGBN1
LCT2_AREXBN5
6
LCT1_WGBN2
LCT1_AREXBN6
LCT2_WGBN2
LCT2_AREXBN6
7
LCT1_WGBN3
LCT1_AREXBN7
LCT2_WGBN3
LCT2_AREXBN7
8
LCT1_WGBN4
LCT1_AREXBN8
LCT2_WGBN4
LCT2_AREXBN8
9
LCT1_WGBN5
LCT1_AREXBN9
LCT2_WGBN5
LCT2_AREXBN9
10
LCT1_WGBN6
LCT1_AREXBN10
LCT2_WGBN6
LCT2_AREXBN10
11
LCT1_BXN0
LCT1_AREXBN11
LCT2_BXN0
LCT2_AREXBN11
12
LCT1_BXN1
STA1<1>
LCT2_BXN1
0
13
LCT1_BXN2
STA1<2>
LCT2_BXN2
0
14
LCT1_BXN3
STA2<1>
LCT2_BXN3
0
15
LCT1_BXN4
STA2<2>
LCT2_BXN4
0
Table 19
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIFO1
LCT1_FLAG
LCT1_CPATBN0
LCT1_CPATBN1
LCT1_CPATBN2
LCT1_CPATBN3
LCT1_CPATBN4
LCT1_CPATBN5
LCT1_CPATBN6
LCT1_CPATBN7
LCT1_BENDBN
LCT1_HSBN0
LCT1_HSBN1
LCT1_HSBN2
LCT1_HSBN3
LCT1_HSBN4
LCT1_HSBN5
Cathode FIFO Buffers
FIFO2
FIFO3
LCT1_HSBN6
LCT2_FLAG
LCT1_HSBN7
LCT2_CPATBN0
LCT1_CBXNBN0
LCT2_CPATBN1
LCT1_CBXNBN1
LCT2_CPATBN2
LCT1_CBXNBN2
LCT2_CPATBN3
LCT1_CBXNBN3
LCT2_CPATBN4
LCT1_CBXNBN4
LCT2_CPATBN5
LCT1_RESBN0
LCT2_CPATBN6
LCT1_RESBN1
LCT2_CPATBN7
LCT1_RESBN2
LCT2_BENBN
LCT1_RESBN3
LCT2_HSBN0
LCT1_RESBN4
LCT2_HSBN1
STB1<1>
LCT2_HSBN2
STB1<2>
LCT2_HSBN3
SyncEr
LCT2_HSBN4
0
LCT2_HSBN5
FIFO4
LCT2_HSBN6
LCT2_HSBN7
LCT2_CBXNBN0
LCT2_CBXNBN1
LCT2_CBXNBN2
LCT2_CBXNBN3
LCT2_CBXNBN4
LCT2_RESBN0
LCT2_RESBN1
LCT2_RESBN2
LCT2_RESBN3
LCT2_RESBN4
0
0
0
0
Table 20
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIFO Status Register
Function
Anode FIFO1_FULL (“1” means full)
Anode FIFO1_EMPTY (“1” means empty)
Anode FIFO2_FULL (“1” means full)
Anode FIFO2_EMPTY (“1” means empty)
Anode FIFO3_FULL (“1” means full)
Anode FIFO3_EMPTY (“1” means empty)
Anode FIFO4_FULL (“1” means full)
Anode FIFO4_EMPTY (“1” means empty)
Cathode FIFO1_FULL (“1” means full)
Cathode FIFO1_EMPTY (“1” means empty)
Cathode FIFO2_FULL (“1” means full)
Cathode FIFO2_EMPTY (“1” means empty)
Cathode FIFO3_FULL (“1” means full)
Cathode FIFO3_EMPTY (“1” means empty)
Cathode FIFO4_FULL (“1” means full)
Cathode FIFO4_EMPTY (“1” means empty)
10. JTAG Chain
TMB logic is based on Altera EPF10KA PLDs, two EPF10K50VRC240-1 for anode and
cathode preprocessing, and EPF10K30AQC240-1 for VME interface and control logic.
Configuration data may be downloaded into all PLDs via either JTAG interface or from
serial EPROMs Altera EPC2LC20. Each of three EPROM may also be programmed via
JTAG interface. DIP switch S4 defines the JTAG chain. When contacts 1 and 4 of S4 are
connected, and 2 and 3 disconnected, there are only PLDs in JTAG chain, and the order
of files to be downloaded from Altera Max+Plus II Programmer via JTAG cable
should be:
Chip: EPF10K50V tmbw.sof
Chip: EPF10K50V tmbs.sof
Chip: EPF10K30A tmbvme.sof
When contacts 1 and 4 are disconnected, and 2 and 3 connected, there are only EPROMs
in JTAG chain, and the order of files to be downloaded from Altera Max+Plus II
Programmer via JTAG cable should be:
Chip: EPC2 tmbw.pof
Chip: EPC2 tmbs.pof
Chip: EPC2 tmbvme.pof
11. How to initialize and test TMB
For initialization after power up:
- Send “Reset TMB internal logic” VME command
- Send “Reset Anode and Cathode FIFO Buffers” VME command
- Program CSR1
- Program CSR2, CSR2<5..6>=0
- Read “FIFO Status Register”, there should be aaaa(hex) code (all FIFOs are empty)
For internal registers (CSR1, CSR2, Test Registers<1..8>) test:
- Write 16-bit words to each register, read it back and check data
For testing without connection to ALCT and CLCT cards:
- Send “Reset TMB internal logic” VME command
- Send “Reset Anode and Cathode FIFO Buffets” VME command
- Program CSR1, CSR1<0..1>=0, CSR1<2>=1, CSR1<5..15>=0
- Program CSR2, CSR2<5..6>=0
- Program Test Registers<1..8>
- Read “FIFO Status Register”, there should be aaaa(hex) code (all FIFOs are empty)
- Send “Run Test” VME command
- Read “FIFO Status Register”
- Read FIFO Buffers
12. Front Panel
There are on the front panel:
LEMO Connectors:
- EXT (External Trigger Input, NIM)
- INT (Internal Trigger Output, NIM)
- ACQ (ACQUIRE, Input, NIM)
- CLK (CLOCK, Output, NIM)
- I1, I2 (Two reserved Inputs, NIM)
- O1, O2 (Two reserved Outputs, NIM)
10-pin JTAG connector
LEDs:
- +3.3V, +5V, -5.2V Power (green)
- A1 (ALCT1), A2 (ALCT2), C1 (CLCT1), C2 (CLCT2) (red) (Flag bits – input
muons from LCT cards)
- M1, M2 (Flag bits – output muons to Port Card) (green)
- DMT (Flag bit – output data word to DAQ Motherboard) (green)
- INT (LCT found) (green)
- VME Access (yellow), JTAG Access (yellow)
References
[1] J.Kubic. LCT99 Prototype Design. Version 1.1. March 5, 1999. Available at:
ftp://hepsun0.physics.ucla.edu/pub/cms/lct99/documentation/
lct99_spec.doc