CSE493/593 Midterm Exam Fall 2015
1. 16 points
a. Why do we gradually increase the size of the inverters in buffer design? Why not give the
output of a circuit to one large inverter?
Ans: Minimize total propagation delay.
b. Redesign a 6 input NAND gate using only 2-input gates (preferably NAND and NOR).
Which one is better? (your new design or the original NAND). Explain why?
Ans: The second design is better because the fan in is smaller and the delay will be
reduced.
c. Consider the static CMOS gate shown in Fig.1. Assume Vdd = 2.5V and VTn = 0.5V. Will
the threshold voltages of the two NMOS transistors be the same? If yes, why? If not, why
not?
Ans: No, the threshold voltages are not the same, due to body effect on the first NMOS in
the PDN. So the threshold of B will higher.
d. In CMOS, if we increase the load capacitance of an inverter, how does it affect the short
circuit power (increase or decrease)? Why?
Ans: It will reduce the short circuit power. If the load capacitance is large, then the ouput
fall time will be significantly larger than the input time. Under this circumstances, the
input moves through the transient region before the output starts to change. So the short
circuit power will be reduced.
2. Consider the function Y = A'BC + AB'C + ABC' 10 points
a. Implement the above expression in compound CMOS logic style (PUN and PDN).
CSE493/593 Midterm Exam Fall 2015
b. Implement the above expression in Transmission logic style.
3. 10 points
Calculate the noise margin below. (VOL = 0.5, VIL = 3, VOH = 4, VIH = 3.8)
Ans:
NML = VIL -VOL= 2.5
NMH = VOH –VIH= 0.2
CSE493/593 Midterm Exam Fall 2015
4.
12 points
a. Size for performance with equal rise and fall times
Ans: For sizing with equal rise and fall time we have to make sure that in each path
the size of PMOS is 3 times the size of NMOS
So for PMOS:
A:6, B:12, C:12, D:6
For NMOS:
A:2, B:2, C:2, D:1
b. Size for performance only
For PMOS:
A:2, B:4, C:4, D:2
For NMOS:
A:2
B:2, C:2, D:1
c. Size the NMOS and PMOS devices so that the output resistance is the same as that of
an inverter with an NMOS W/L = 6 and PMOS W/L = 10.
PMOS:
A: 20 B: 40 C:40 D:20
NMOS:
A:12
B:12 C:12 D:6
5. 12 points
Briefly specify the three types of power consumption in CMOS technology. Give the factors
that affect each of these (Hint: you may specify the equations in explaining).
CSE493/593 Midterm Exam Fall 2015
Ans:
1. Dynamic Power Consumption: dynamic power is consumed due to the CL gets charged
through PMOS and discharged through NMOS;
2. Short circuit power consumption is due to finite slope of the input signal causes a direct
current path between VDD and GND for a short period of time during switching when
both the NMOS and PMOS transistors are conducting.
3. Static power consumption is due to the current that flows between the supply rails in the
absence of switching activity.
6. 12 points
Draw a rising edge triggered D flip-flop using Transmission gates. Explain how it functions.
Ans: The multiplexer is implemented using transmission gates as discussed in the previous
section. When clock is low, T1 is on and T2 is off, and the D input is sampled onto node QM.
During this period, T3 is off and T4 is on and the cross-coupled inverters (I5, I6) hold the state
of the slave latch. When the clock goes high, the master stage stops sampling the input and
goes into a hold mode. T1 is off and T2
7. 12 points
Design a pass-transistor network that implements the following Boolean function
D = A’BC + AB’C + ABC’ + (ABC)’
CSE493/593 Midterm Exam Fall 2015
8. 16 points
a. In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with input
capacitance Ci = 10fF), you decide to introduce a three-staged buffer. Assume that the
propagation delay of a minimum size inverter is 70 ps. Also assume that the input
capacitance of a gate is proportional to its size. Determine the sizing of the three
additional buffer stages that will minimize the propagation delay. (N = 4 in total)
Ans: In this problem, the number of stages N = 4, CL = 20pF, Ci = 10fF.
Minimum delay occurs when the delay through each buffer is the same. This can be
achieved by sizing the buffers as 6.7(W/L), (6.7)^2(W/L) , (6.7)^3(W/L)respectively
b. If you could add any number of stages to achieve the minimum delay, how many stages
would you insert? What is the propagation delay in this case?
(e = 2.718, 1pF = 10−12F, 1fF = 10−15F)
To achieve minimum delay, Let
So we can obtain N=7.6 .
We choose N=7
When N=7,
Tp = Ntp0(1 + f/λ) =1.9ns