MOS LOGIC FAMILIES
In our last lecture, we were introduced to digital logic. We saw that the building blocks of
digital circuitry are logic gates. We now take on the task of investigating how MOSFETs are
used to realise some of the common logic gates. This is the MOSFET switching application we
have introduced before. MOS logic uses NMOS and PMOS to implement logic gates. One
needs to know the operation of the FET and MOS transistors to understand the operation of
MOS logic circuits. In addition, we have CMOS, CVS and Dynamic logic arising. As will
become evident later, CMOS has of late become the hugely dominant force in logic integration.
MOSFETs are not the only components used for making logic devices. Another common
device used is the Bipolar Junction Transistor (BJT), not tackled in this course. However,
MOSFETs are preferred because they are:



Simple and cheap to fabricate
Consume very little power
More circuit elements are possible.
When dealing with logic families, the following terms are useful:
VCC: The voltage applied to the power pin(s). In most cases the voltage the device needs to
operate at. For MOS, it is +5V.
VIH [High State Input Voltage Input]: The minimum positive voltage applied to the input which
will be accepted by the device as a logic high.
VIL [Low Sate Input Voltage]: The maximum positive voltage applied to the input which will be
accepted by the device as a logic low.
VOL [Low State Output Voltage]: The maximum positive voltage from an output which the device
considers will be accepted as the maximum positive low level.
VOH [High Sate Output Voltage]: The positive voltage from an output which the device considers
will be accepted as the minimum positive high level.
VT [Threshold Voltage]: The voltage applied to a device which is "transition-Operated", which
cause the device to switch. May also be listed as a '+' or '-' value.
I illustrate the relevance of these terms in figure 1 from which we define another term, Noise
Margin. This is the amount of “noise” a signal can tolerate going from an output to an
input.
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Figure 1: Making Sense of Logic Determining Voltages
For your benefit, let me illustrate the corresponding numerical values for the different logic families.
(You should get interested and try to find out the unfamiliar families at least by name)!
Figure 2: Voltage Level Comparison
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5.1 NMOS Logic
NMOS logic uses n-channel MOSFETs exclusively.
5.1.1 NMOS Inverter
The basic N-channel MOSFET used as a switch is illustrated below: (a) symbol; (b) circuit
model; (c) N-MOS inverter operation.
Figure 3: NMOS Inverter
When input is LOW, NMOS transistor does not conduct, and thus output is HIGH but when
the input is HIGH, NMOS transistor conducts and thus output is LOW.
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5.1.2 NMOS NOR Gate
Figure 4: NMOS NOR
Verify the truth table for the above logic circuit
5.1.2 NMOS NAND Gate
VOUT
Figure 5: NMOS NAND
Verify that both MOSFETs can conduct current only when both inputs are high, and hence
derive the truth table.
Note:
While NMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a
resistor, so the whole circuit can be made with nMOSFETs), it has several shortcomings as
well. The worst problem is that a DC current flows through an NMOS logic gate when the
PDN is active, that is whenever the output is low. This leads to static power dissipation even
when the circuit sits idle. Also, NMOS circuits are slow to transition from low to high.
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5.2 PMOS Logic
We now illustrate the P-channel MOSFET used as a switch: (a) symbol; (b) circuit model for
OFF and ON; (c) P-MOS inverter circuit.
Figure 6: PMOS Inverter
The other logic implementations follow through as for NMOS. Try to figure these out.
5.3 CMOS Logic
CMOS or Complementary Metal Oxide Semiconductor logic is built using both NMOS and
PMOS. This comes with several advantages over the earlier two. CMOS logic is faster and
consumes less power. However, it requires more complex fabrication. Recall that NMOS
conducts when its input is HIGH while PMOS conducts when its input is LOW. I hope you have
read up CMOS characteristics. Take another look at its physical structure below and then we
head straight to the Gates!
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Figure 7: CMOS Physical Structure
5.3.1 CMOS Inverter
Figure 8: CMOS Inverter
The CMOS inverter is designed to use one NMOS and one PMOS, both having an equal
threshold voltage (in magnitude). Note that the high and low states correspond to 0 and VDD.
Consider the case when VIN =VDD. Q1 (PMOS) is off while Q2 (NMOS) is on and VOUT =0. (Note
that the PMOS is the driver circuit). When VIN =0, Q1 (PMOS) is ON while Q2 (NMOS) is off.
The output VOUT =VDD. Note that in both cases, there is no static current flowing through the
inverter since at any one time; there is no continuous path to ground. Since the output is an
opposite of the input, this is an inverter.
Easy to recall: OFF- switch open, ON-Switch closed, with the switches modelled by the
drain-source resistance of the respective transistors.
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5.3.2 CMOS NAND Gate
Figure 9: CMOS NAND
5.3.3 CMOS NOR Gate
Figure 10: CMOS NOR
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5.4 Dynamic Logic
The above logic types are all static, because the voltage of each node is well defined at any
given time and no node is left floating. Static circuits do not need clocks (periodic timing
signals) for their operation. Dynamic circuits on the other hand rely on the storage of signal
voltages on parasitic capacitances at certain nodes. Since charge leaks away with time, the
circuits need to be periodically refreshed.
Read about application of static and dynamic logic in SRAM and DRAM
Dynamic logic requires a minimum clock rate fast enough that the output state of each
dynamic gate is used before it leaks out of the capacitance holding that state, during the
part of the clock cycle that the output is not being actively driven. Dynamic logic (properly
designed) is over twice as fast as normal logic.
Consider the dynamic logic implementation of a NAND Gate below:
QP
Qe
Figure 11: Dynamic Logic NAND Gate
The dynamic logic circuit requires two phases. The first phase, when Clock is low, is called the
setup phase or the precharge phase and the second phase, when Clock is high, is called the
evaluation phase. In the setup phase, Qp is on while Qe is off and the output is driven high
unconditionally (no matter the values of the inputs A and B). The capacitor, which represents
the load capacitance of this gate, becomes charged up to VDD. Because Qe is off, it is impossible
for the output to be driven low during this phase.
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During the evaluation phase, Clock is high. If A and B are also high, the output will be pulled
low. Otherwise, the output stays high (due to the load capacitance).
What are the shortcomings of Dynamic Logic?
5.5 CVS Logic and Cascade Buffers
Read and Make Notes-simple stuff only
5.6 MOS Power Scaling/Delaying
Scaling deals with increasing the number of logic gates current handling capacity in a given
circuit or without increase in physical size. It comes with a possibility of increase in power
dissipation. Until mid 80s technology was mixed i.e. NMOS, bipolar and some CMOS. The
Supply voltage could not be scaled without increasing power dissipated. With the advent of
CMOS, VDD could be scaled as illustrated by the characteristic graphs below:
In the above ideal scaling, V scales to aV, L scales to aL, C scales to aC, i scales to ai , Delay =
CV/I scales as a and energy = CV2 scales as a3.
However, the processor power continued to grow when VDD was scaled due to the need for fast
processing speeds. Every 2 years, the number of transistors doubles and transistors get faster.
As a result, low power design techniques are now improvised in modern digital circuitry:
•
Clock gating: If a section is idle, the clock is removed, removing clock power clock thus
preventing any internal node from transitioning.
•
Creation of system power states by turning on subsystems only when they are needed.
•
Power supply gating: Done to remove leakage power but slows down the circuit. It is
done by adding a series resistance to the supply.
•
Try to provide a couple of operating points such that applications can control speed and
energy e.g Intel Speed Step in laptop processors where there are 2 performance/power
points.
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