EGR 277
Digital Logic
File: N277Lsu7
Lecture #7
Reading Assignment: Chapter 4 in Digital Design, 3rd Edition by Mano
Chapters 1-3: Basic tools (number systems, expressions, gates, minimization methods. etc)
Chapter 4 – Combinational Logic Circuits (designed circuits and commercially-available circuits)
Design Procedure for Combinational Logic Circuits
In general, we might want to design a combinational logic circuit with N inputs and M outputs, as shown
below.
N inputs
Logic
Gates
M outputs
Design Procedure:
1. State the problem
2. Determine the required inputs and outputs
3. Assign variables to the inputs and outputs
4. Derive the truth table
5. Simplify the output expressions
6. Implement the expressions with logic gates
Example: Design a prime number indicator
Example:
•
•
•
•
•
Code Converters
BCD to excess-3 (try this one in class)
ASCII to EBCDIC
Binary to 2’s complement
Excess-3 to reflected
BCD to 9’s complement (try this one in class)
Example: Half-adder – adds 2 bits with no carry in and one carry out
Example: Full-adder – adds 2 bits with one carry in and one carry out
• Illustrate the SOP implementation
• Illustrate the XOR implementation
• Show how a full adder can be constructed using two half adders
• 4-bit adder using 4 full adders
• 7483 4-bit adder (explain “look-ahead carry” circuit)
• Handout: 7483 data sheet
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Combinational Logic Using MSI and LSI devices
We have the capability to design our own combinational logic circuits, but circuits of common interest
are probably available commercially. Commercial devices can perform complex functions using perhaps
a single IC, thus saving space. They are typically faster that equivalent circuits that we might build using
discrete logic gates. It might be a good idea to browse through a Logic Data Book to see what is
available. A few devices are listed below.
Assortment of commercially available combinational logic devices
TTL Device
Number
7483
7485
74139
74137
74159
74145
74147
74151
74150
74184
7447
7448
74280
Description
4-bit adder with fast carry
4-bit magnitude comparator
2-line-to-4-line decoder/demultiplexer
3-line-to-8-line decoder/demultiplexer
4-line-to-16-line decoder/demultiplexer
BCD-to-decimal decoder
Priority encoder
8 x 1 multiplexer
16 x 1 multiplexer
BCD-to-binary converter
BCD-to-7-segment decoder/driver (common anode)
BCD-to-7-segment decoder/driver (common cathode)
9-bit odd/even parity generator
Decoders
An N-bit decoder has 2N outputs, only one of which may be activated at a given time.
If the device is active-HIGH , then only one output may be HIGH at any time.
If the device is active-LOW , then only one output may be LOW at any time.
Example: A 3-bit decoder might also be called a 3-line-to-8-line decoder or a 3x8 decoder.
The block diagram is shown below:
D0
D1
x
22
D2
3
x
8
D3
1
Input
y
2 Decoder
Only one output is activated (HIGH)
D4
Code
0
z
2
D5
D6
D7
Simple decoder design:
D0 = 1 only when x = 0 , x = 0 , and z = 0, so
D0 = x’y’z’
D1 = x’y’z
Etc (draw the logic diagram)
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Active-LOW versus Active-HIGH decoders
Enable lines – essentially act as ON/OFF switches
Example: Show the truth table and block diagram for an active-LOW 2x4 decoder with an enable line, E.
Implementing Boolean functions using decoders
Note that the decoder outputs for active-HIGH decoders are simply minterms, so
F = Σ(minterms) = Σ(active-HIGH decoder outputs)
Example: Implement f(A,B,C) = Σ(0, 3, 5, 6) using a 3 x 8 decoder with active-HIGH outputs
Note that the decoder outputs for active-LOW decoders are simply maxterms, so
F = Π(maxterms) = Π (active-LOW decoder outputs)
Example: Implement f(A,B,C) = Σ(0, 3, 5, 6) using a 3 x 8 decoder with active-LOW outputs
Decoder IC’s
Handout: 74155 (dual 2x4 decoder/single 3x8 decoder)
Note: The 74156 is similar to the 74155 except that it has open-collector outputs instead of totem-pole
outputs.
Show how to connect the 74155 as a 2x4 decoder and also as a 3x8 decoder.
Show how to use two 74155’s to form a 4x16 decoder.