Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
80386DX
Features
•
It supports 8/16/32 bit data operands
•
It has 32-bit internal registers
•
It supports 32-bit data bus and 32-bit non-multiplexed address bus
•
It supports
–
Physical Address of 4GB
–
Virtual Address of 64TB
–
Maximum Segment size of 4GB
•
It operates in 3 different modes
–
Real
–
Protected
–
Virtual 8086
•
MMU provides virtual memory, paging and 4 levels of protection
•
Clock Frequency : 20,25 and 33MHz
•
It has 132 pin package
Architecture of 80386
UQ: Draw the block diagram of the 80386 DX Processor and explain each block in brief
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
The internal architecture of 80386 is divided into three sections:
1.
Central Processing Unit
2.
Memory Management Unit
3.
Bus Interface unit
Central Processing Unit
•
The CPU is further divided into Instruction Unit and Execution Unit
•
Instruction Unit:
–
It decodes the opcode bytes received from the 16-byte instruction queue and arranges them into a 3-decoded instruction queue.
–
After decoding it is passed to control section for deriving necessary control signals
•
Execution Unit:
–
It has 8 general purpose and 8 special purpose registers which either handles data or addresses
–
The 64-bit barrel shifter increases the speed of all shift, rotate, multiply and divide operations
–
The multiply/divide logic implements the bit-shift-rotate algorithms to complete the operations in minimum time(Even 32bit multiplication is done in 1µs)
•
Elements of Execution Unit
1.
Arithmetic/logic unit (ALU): Performs the operation identified by ADD, SUB, AND, etc.
2.
Flags register: Holds status and control information
3.
General-purpose registers: Holds address or data information
4.
Control ROM: Contains microcode sequences that define operations performed by machine instructions
5.
Special multiply, shift, and barrel shift hardware: Accelerate multiply, divide, and rotate operations
Memory Management Unit
•
MMU consists of a segmentation unit and paging unit
•
Segmentation Unit:
–
It allows the use of two address components - segment and offset – for relocability and sharing of data
–
It allows a maximum segment size of 4GB
–
It provides a 4-level protection mechanism for protecting and isolating system’s code and data from those of application program
–
The limit and attribute PLA checks segment limits and attributes at segment level to avoid invalid accesses to code and data in memory segment.
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
•
Paging Unit
–
It organizes physical memory in terms of pages of 4KB size
–
It works under the control of segmentation unit
–
It converts linear addresses into physical addresses
–
The control and attribute PLA checks privileges at page level.
Bus Interface Unit
•
It has a prioritizer to resolve the priority of various bus requests. This controls the access of the bus
•
The address driver drives the bus enable and address signals A
2
– A
31
.
•
The pipeline/bus size unit handles the control signals for pipelining and dynamic bus sizing units
•
The data buffers interface the internal data bus with system bus
Signal Interface of 80386DX
•
Signals are arranged by functional groups.
•
The # symbol indicates active low signal.
•
When no # is present, the signal is active high.
•
Example: M/IO# - High voltage indicates memory selected
- Low voltage indicates I/O selected

Clock (CLK2):
–
It is divided by two internally to generate the internal processor clock.
–
The phase of internal processor clock can be synchronized to a known phase.
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
•
Data Bus (D0 through D31):
–
It has three-state bidirectional signals.
–
It can transfer data on 32- and 16-bit buses using a data bus sizing feature.
•
Address Bus (A2 through A31)
•
These three-state outputs provide memory or I/O port addresses.
•
It can access 4GB of physical memory from 00000000H to FFFFFFFFH
•
Of the total 32-bits, only higher 30 are released by MP
•
A1 & A0 are used internally by MP to produce 4 bank enable signals(BE3# - BE0#)
•
Byte Enable Outputs( BE0# -- BE3#)
• enable 4 memory banks
• indicates which bytes of the 32-bit data bus are involved with the current transfer.
•
BE0# applies to D0-D7
•
BE1# applies to D8-D15
•
BE2# applies to D16-D23
•
BE3# applies to D24-D31
•
No. of Byte Enables asserted indicates physical size of operand being transferred (1, 2, 3, or 4 bytes).
1
1
0
1
0
0
BE3#
1
1
1
1
0
1
0
0
0
0
0
BE2#
1
1
1
0
1
0
0
1
0
0
0
BE1#
1
1
0
1
1
0
1
1
0
1
0
BE0#
1
0
1
1
1
4
Operation
No Operation
Bank0 (8-bit)
Bank1 (8-bit)
Bank2 (8-bit)
Bank3 (8-bit)
Bank 0,1 (16-bit)
Bank 1,2 (16-bit)
Bank 2,3 (16-bit)
Bank 0,1,2(24-bit)
Bank 1,2,3(24-bit)
Bank 0,1,2,3 (32-bit)

Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
Bus Cycle Definition Signals (W/R#, D/C#, M/IO# , LOCK#)
– three-state outputs
–
W/R# :distinguishes b/w write and read cycles.
–
D/C# :distinguishes b/w data and control cycles.
–
M/IO# :distinguishes b/w memory and I/O cycles.
–
LOCK# :distinguishes b/w locked and unlocked bus cycles. It enables CPU to prevent other bus masters (like coprocessor) from gaining the control of system bus.
These control signals are decoded by the bus control logic to decide which bus cycle to be performed:
0 0
0 0
0 Interrupt
Acknowledge
1 Inactive
Yes
--
0
0
1
1
0 I/O Data Read
1 I/O Data Write
No
No
1 0 0 Memory Code
Read
1 HALT
No
1 0 No
1 1 0 Memory Data
Read
Sometimes
1 1 1 Memory Data
Write
Sometimes
Bus Control Signals (ADS#,READY#,NA#,BS16#):
– indicates when a bus cycle has begun and allow other system hardware to control address pipelining, data bus width and bus cycle termination.
–
ADDRESS STATUS (ADS#) : indicates that a valid address is driven at 80386DX pins.
–
TRANSFER ACKNOWLEDGE (READY#) : indicates that the previous bus cycle is complete and bus is ready for next bus cycle. It is useful for interfacing slow peripherals
–
NEXT ADDRESS REQUEST (NA#) :
–
This is used to enable address pipelining.
–
It indicates that the system is prepared to accept the next address even if the end of current cycle is not being acknowledged on READY#.
–
BUS SIZE 16 (BS16#) :
–
Asserting this input constrains current bus cycle to use only D0-D15 of data bus.
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
Bus Arbitration Signals (HOLD, HLDA)
•
BUS HOLD REQUEST (HOLD):
–
This input indicates some other device requires bus mastership.
–
HOLD must remain asserted as long as any other device is a local bus master.
–
HOLD is not recognized while RESET is asserted. (i.e. RESET has priority over
HOLD and places the bus into an idle state rather than hold acknowledge state)
–
HOLD is level-sensitive.
•
BUS HOLD ACKNOWLEDGE (HLDA):
–
This output indicates 80386 has relinquished control of its local bus in response to
HOLD asserted and it is in Bus Hold Acknowledge state.
–
This state offers near-complete signal isolation ( It is the only signal being driven by
80386)
–
The other output signals (D0-D31, BE0#-BE3#, A2-A31, W/R#, D/C#,M/IO#, LOCK# and ADS#) are in a high-impedance state so the requesting bus master may control them.
Coprocessor Interfacing
Intel 387DX numeric coprocessor is I/O mapped
•
As Intel386DX begins supporting a coprocessor instruction, it tests the BUSY# and
ERROR# signals to determine if the coprocessor can accept its next instruction
•
Intel 387DX can be given its command opcode immediately
COPROCESSOR REQUEST (PEREQ) :
•
This input signal indicates a coprocessor request for a data operand to be transferred to/from memory by Intel386 DX.
•
In response, Intel 386DX transfers information between the coprocessor and memory
•
Since Intel386 DX has internally stored the coprocessor opcode being executed, it performs the requested data transfer with the correct direction and memory address.
•
PEREQ is level-sensitive
COPROCESSOR BUSY (BUSY#) :
•
This input indicates that coprocessor is still executing an instruction and is not yet able to accept another.
•
This sampling of BUSY# input prevents overrunning the execution of a previous coprocessor instruction.
•
BUSY# is level-sensitive
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
•
COPROCESSOR ERROR (ERROR#) :
•
This input signal indicates that the previous coprocessor instruction generated a coprocessor error of a type not masked by coprocessor's control register.
•
This input is automatically sampled by Intel386 DX when a coprocessor instruction is encountered, and if asserted it generates exception 16 to access the error-handling software.
•
ERROR# is level-sensitive
Interrupt Signals (INTR, NMI, RESET)
•
MASKABLE INTERRUPT REQUEST (INTR):
–
This input indicates a request for interrupt service, which can be masked by Flag
Register IF bit.
–
When processor responds to INTR input, it performs two interrupt acknowledge cycles and at the end of second, it latches an 8-bit interrupt vector on D0-D7 to identify source of interrupt.
–
INTR is level-sensitive
–
To assure recognition of an INTR request, INTR should remain asserted until the first interrupt acknowledge bus cycle begins.
•
NON-MASKABLE INTERRUPT REQUEST(NMI):
–
This input indicates a request for interrupt service which cannot be masked by software.
–
Because of fixed NMI slot, no interrupt acknowledge cycles are performed when processing NMI.
–
NMI is rising edge-sensitive
–
Once NMI processing has begun, no additional NMIs are processed until the next
IRET instruction, which is typically the end of the NMI service routine.
•
RESET (RESET) :
–
This input signal suspends any operation in progress and places the Intel386 DX in a known reset state.
–
The Intel386 DX is reset by asserting RESET for 15 or more CLK2 periods
–
When RESET is asserted, all other input pins are ignored, and all other bus pins are driven to an idle bus state.
–
If RESET and HOLD are both asserted at a point in time, RESET takes priority.
–
RESET is level-sensitive
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
•
Vcc: These are system power supply lines
•
GND: These are return lines for the power supply
Programming Model
•
The basic programming model consists of the following aspects:
–
Registers
–
Instruction Set
–
Addressing Modes
–
Data Types
–
Memory Organization
–
Interrupts and Exceptions
•
Register Overview
•
The Intel386 DX has 32 register resources in the following categories:
–
General Purpose Registers
–
Segment Registers
–
Instruction Pointer and Flags
–
Control Registers
–
System Address Registers
–
Debug Registers
–
Test Registers
General Purpose Registers
• hold data or address values.
• support data of 1, 8, 16, 32 and 64 bits.
•
32-bit registers : EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP.
•
The least significant 16 bits of the registers can be accessed as in 8086 with names of the registers AX, BX, CX, DX, SI, DI, BP, and SP.
•
When accessed as a 16-bit operand, the upper 16 bits of the register are neither used nor changed.
•
8-bit operations can be performed with AL, BL, CL and DL.
•
The higher bytes are AH, BH, CH and DH
•
The individual byte accessibility offers flexibility for data operations.
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Ms Vincy Joseph
Segment Registers
Advanced Microprocessor TE CMPNA/B
•
The segment registers
–
CS indicates the current code segment
–
SS indicates the current stack segment
–
DS, ES, FS and GS indicate four current data segments.
•
On any data reference the DS-pointed data segment is assumed by default.
•
In order to access any other data segment, an override directive is used
Instruction Pointer
•
It is a 32-bit register named EIP.
•
EIP holds the offset of the next instruction to be executed.
•
The offset is always relative to the base of the code segment (CS).
•
The lower 16 bits of EIP contain the 16-bit instruction pointer named IP, which is used by 16-bit addressing.
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Ms Vincy Joseph
Flag Register
Advanced Microprocessor TE CMPNA/B
•
Bit 17 (VM Bit, Virtual Mode):
–
When VM bit is set, the processor will be working in Virtual 8086 mode
•
Bit 16 (RF Bit, Resume Flag):
–
The RF flag is used in conjunction with the debug register breakpoints.
–
When RF is set, it causes any debug fault to be ignored on the next instruction. RF is then automatically reset at the successful completion of every instruction
•
Bit 15 : Reserved
•
Bit 14 (NT Bit, Nested Task):
–
This flag applies to Protected Mode.
–
NT is set to indicate that the execution of this task is nested within another task.
–
If set, it indicates that the current nested task's Task State Segment (TSS) has a valid back link to the previous task's TSS.
•
Bit 13,12 (IOPL Bit, Input/output Privilege):
– maximum CPL (current privilege level) value permitted to execute I/O instructions without generating an exception 13 fault or consulting the I/O
Permission Bitmap.
•
Bit 11 (OF Bit, Overflow Flag):
–
OF is set if the operation resulted in a signed overflow.
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
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Bit 10 (DF Bit, Direction Flag):
–
DF defines whether ESI/EDI registers post-decrement or post-increment during the string instructions.
–
Post-increment occurs if DF is reset.
–
Post-decrement occurs if DF is set.
•
Bit 9 (IF Bit, Interrupt Enable Flag):
–
When IF =1 the processor allows recognition of external interrupts on INTR pin
•
Bit 8 (TF Bit, Trap Enable Flag):
–
When TF =1 the processor enables the single step mode for debugging.
•
Bit 7 (SF Bit, Sign Flag):
–
SF is set if the high-order bit of the result is set, it is reset otherwise.
•
Bit 6 (ZF bit, Zero Flag):
–
ZF is set if all bits of the result are 0.
•
Bit 4 (AF Bit, Auxiliary Carry Flag):
–
Auxiliary Flag is used to simplify the addition and subtraction of packed BCD numbers.
–
AF is set if the operation resulted in a carry out of bit 3 (addition) or a borrow into bit 3 (subtraction).
–
Otherwise AF is reset.
–
AF is only for bit 3.
•
Bit 2 (PF Bit, Parity Flag):
–
PF is set for even parity.
•
Bit 0 (CF Bit, Carry Flag):
–
CF is set for 8-, 16- or 32-bit operations if it results in a carry out of (addition), or a borrow into (subtraction) the high-order bit.
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
Control Registers
•
Intel386 DX has three control registers of 32 bits, CR0, CR2 and CR3, to hold machine state of a global nature
•
These registers along with System Address Registers hold machine state that affects all tasks in the system
•
To access Control Registers, load and store instructions are defined
CR0 : Machine Control Register
•
CR0 contains 6 defined bits for control and status purposes.
•
The low-order 16 bits of CR0 is defined as Machine Status Word
•
To operate only on the low-order 16-bits of CR0, LMSW and SMSW instructions are used.
•
For 32-bit operations the system should use MOV CR0, Reg instruction.
•
Bit 31 (PG Bit, Paging Enable) : The PG bit is set to enable the on-chip paging unit.
•
Bit 4 (Reserved) : This bit is reserved by Intel.
•
Bit 3 (TS Bit, Task Switched) : TS is automatically set whenever a task switch operation is performed.
•
Bit 2 (EM Bit, Emulate Coprocessor) :
•
This bit is set to cause all coprocessor opcodes to generate a Coprocessor Not
Available fault (exception 7).
•
Bit 1 (MP Bit, Monitor Coprocessor) :
•
The MP bit is used with TS bit to determine if the WAIT opcode will generate a
Coprocessor Not Available fault (exception 7).
•
When both MP = 1 and TS= 1, the WAIT opcode generates a trap which checks for the coprocessor availability.
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Ms Vincy Joseph Advanced Microprocessor
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Bit 0 (PE Bit, Protection Enable) :
•
The PE bit is set to enable the Protected Mode.
•
If PE is reset, the processor operates in Real Mode.
CR1 : Reserved
•
CR1 is reserved for use in future Intel processors
CR2 : Page Fault Linear Address
•
CR2 holds the 32-bit linear address that caused the last page fault detected.
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CR3 : Page Directory Base Address
•
CR3 contains the physical base address of the page directory table.
•
The Intel386 DX page directory table is always page-aligned (4 Kbyte-aligned).
•
Thus the lowest twelve bits of CR3 are ignored.
•
A task switch through a TSS invalidates all page table entries in paging unit cache.
System Address Registers
•
Four special registers are defined to reference the tables.
•
These tables or segments are:
–
GDT (Global Descriptor Table)
–
IDT (Interrupt Descriptor Table)
–
LDT (Local Descriptor Table)
–
TSS (Task State Segment)
•
The addresses of these tables and segments are stored in special registers, the System
Address and System Segment Registers.
•
These registers are named GDTR, IDTR, LDTR and TR, respectively
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Ms Vincy Joseph
GDTR and IDTR
Advanced Microprocessor
•
These registers hold:
–
32-bit linear base address and
–
16-bit limit of GDT and IDT respectively.
•
GDT and IDT segments are global to all tasks in the system.
LDTR and TR
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•
These registers hold 16-bit selector for
–
LDT descriptor and
–
TSS descriptor
•
Since they are task specific, they are defined by selector values stored in system segment registers.
•
A system descriptor register, which is not visible to programmer, is associated with each system segment register
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
Debug Registers
UQ: Explain the debug registers of Pentium
UQ: Explain the Debug Registers of 80386 DX processor
•
Debugging of 80386 allows data access breakpoints as well as code execution breakpoints.
•
80386 contains 6 debug registers to specify
–
4 breakpoints
–
Breakpoint Control options
–
Breakpoint Status
Linear Breakpoint Address Registers
•
The breakpoint addresses specified are 32-bit linear addresses
•
While debugging, Intel 386 h/w continuously compares the linear breakpoint addresses in
DR0-DR3 with the linear addresses generated by executing software.
Debug Control Register
•
LEN i
(i=0 - 3): Breakpoint Length Specification Bits:
•
2 bit field for each breakpoint
•
Specifies length of breakpoint fields
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
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The choices of data breakpoints are 1byte, 2bytes & 4bytes
•
For instruction execution breakpoint, the length is 1(beginning byte address)
LEN i
Encoding
•
RW i
(i=0 - 3): Memory Access Qualifier Bit
•
2 bit field for each breakpoint
•
Specifies the type of usage which must occur inorder to activate the associated breakpoint
•
GD : Global Debug Register Access Detect
•
Debug registers can only be accessed in real mode or at privilege level 0 in protected mode
•
GD bit, when set, provides extra protection against any Debug Register access even in Real Mode or at privilege level 0 in Protected Mode.
•
This additional protection feature is provided to guarantee that a software debugger can have full control over the Debug Register resources when required.
•
The GD bit, when set, causes an exception 1 fault if an instruction attempts to read or write any Debug Register.
•
The GD bit is then automatically cleared when the exception 1 handler is invoked, allowing the exception 1 handler free access to the debug registers.
•
GE and LE bit : Exact data breakpoint match, global and local
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
•
If either GE or LE is set, any data breakpoint trap will be reported exactly after completion of the instruction that caused the operand transfer.
•
LE bit is cleared during task switch and is used for task-local breakpoints.
•
GE bit is unaffected during a task switch and remain enabled during all tasks executing in the system.
•
G i and L i
(i=0 - 3): Breakpoint Enable, global and local
•
If either G i
and L i
is set then the associated breakpoint is enabled.
Debug Status Register
•
A Debug Status Register allows the exception 1 handler to easily determine why it was invoked.
•
It can be invoked as a result of one of several events:
1) DR0 Breakpoint fault/trap.
2) DR1 Breakpoint fault/trap.
3) DR2 Breakpoint fault/trap.
4) DR3 Breakpoint fault/trap.
5) Single-step (TF) trap.
6) Task switch trap.
7) Fault due to attempted debug register access when GD = 1.
•
B i
: Debug fault/trap due to breakpoint 0 -3
•
Four breakpoint indicator flags, B0-B3, correspond one-to-one with the breakpoint registers in DR0-DR3.
•
A flag B i
is set when the condition described by DR i
, LEN i
, and RW i
occurs.
•
BD : Debug fault due to attempted register access when GD bit is set
•
This bit is set if the exception 1 handler was invoked due to an instruction attempting to read or write to the debug registers when GD bit was set.
•
BS : Debug trap due to single step
•
This bit is set if the exception 1 handler was invoked due to the TF bit in the flag register being set
•
BT : Debug trap due to task switch
•
This bit is set if the exception 1 handler was invoked due to a task switch occurring to a task having an Intel386 DX TSS with the T bit set.
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Ms Vincy Joseph
Test Registers
Advanced Microprocessor TE CMPNA/B
•
They are used to control the testing of Translation Look-aside Buffer of Intel386 DX.
•
TR6 is the command test register
•
TR7 is the data register which contains the data of Translation Look-aside buffer test
Instruction Set
•
The instruction set is divided into 9 categories of operations:
•
Data Transfer
•
Arithmetic
•
Shift/Rotate
•
String Manipulation
•
Bit Manipulation
•
Control Transfer
•
High Level Language Support
•
Operating System Support
•
Processor Control
•
These instructions operate on either 0,1,2 or 4 operands
• where an operand resides in
•
Register
•
Instruction itself
•
Memory
•
Most zero operand instructions take only one byte
•
One operand instructions are generally two bytes long
•
The average instruction is 3.2 bytes long
•
Since 80386 has a 16-byte queue, an average of 5 instructions are prefetched.
•
The use of 2 operands permits the following types of common instruction:
•
Register to Register
•
Memory to Register
•
Immediate to Register
•
Register to Memory
•
Immediate to Memory
•
The operands can be either 8,16 or 32 bits long
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
Addressing Modes
•
The Intel386 DX provides 11 addressing modes for instructions to specify operands.
•
Register Operand Mode:
•
The operand is located in one of the 8-, 16- or 32-bit general registers.
•
Example : ADD EAX,EBX
•
Immediate Operand Mode:
•
The operand is included in the instruction as part of the opcode.
•
Example : CLI,STI
•
The remaining 9 modes provide a mechanism for specifying the effective address of an operand.
•
The linear address consists of two components:
•
the segment base address and
• an effective address.
•
The effective address is calculated by using four address elements:
•
DISPLACEMENT : An 8-, or 32-bit immediate value
•
BASE : The contents of any general purpose register. It is generally used by compilers to point to the start of the local variable area.
•
INDEX : The contents of any general purpose register except for ESP. The index registers are used to access the elements of an array, or a string of characters.
•
SCALE: The index register's value can be multiplied by a scale factor, either 1, 2,
4 or 8. Scaled index mode is especially useful for accessing arrays or structures.
•
Combinations of these 4 components make up the 9 additional addressing modes
•
The effective address (EA) of an operand is calculated according to the following formula:
EA = Base Register+ (Index Register * Scaling) + Displacement.
•
This calculation can be shown as follows:
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
•
Direct Mode:
•
The operand's offset is contained as part of the instruction as an 8- or 32-bit displacement.
Example: INC Word PTR [500]
•
Register Indirect Mode:
•
A base register will contain the address of operand
•
Example: MOV [ECX], EDX
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
•
Based Mode:
•
A BASE register's contents is added to a DISPLACEMENT to form the operands offset.
•
Example: MOV ECX, [EAX+24]
•
Index Mode:
•
An INDEX register's contents is added to a DISPLACEMENT to form the operands offset. EXAMPLE: ADD EAX, TABLE[ESI]
•
Scaled Index Mode:
•
An INDEX register's contents is multiplied by a scaling factor which is added to a
DISPLACEMENT to form the operands offset.
•
Example: IMUL EBX, TABLE[ESI*4],7
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
•
Based Index Mode:
•
The contents of a BASE register is added to the contents of an INDEX register to form the effective address of an operand.
Example: MOV EAX, [ESI] [EBX]
•
Based Scaled Index Mode:
•
The contents of an INDEX register is multiplied by a SCALING factor and the result is added to the contents of a BASE register to obtain the operands offset.
•
Example: MOV ECX, [EDX*8] [EAX]
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
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Based Index Mode with Displacement:
•
The contents of an INDEX Register and a BASE register's contents and a
DISPLACEMENT are all summed together to form the operand offset.
•
Example: ADD EDX, [ESI] [EBP+00FFFFF0H]
•
Based Scaled Index Mode with Displacement:
•
The contents of an INDEX register are multiplied by a SCALING factor, the result is added to the contents of a BASE register and a DISPLACEMENT to form the operand's offset.
•
EXAMPLE: MOV EAX, LOCALTABLE[EDI*4] [EBP+80]
Data Types
•
The Intel386 DX supports all of the data types commonly used in high level languages:
•
Bit: A single bit quantity.
•
Bit Field: A group of upto 32 contiguous bits, which spans a maximum of four bytes.
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
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Bit String: A set of contiguous bits, on the Intel386 DX bit strings can be up to 4 gigabits long.
•
Byte: A signed 8-bit quantity
•
Unsigned Byte : An unsigned 8-bit quantity.
•
Integer (Word) : A signed 16-bit quantity.
•
Long Integer (Double Word) :
–
A signed 32-bit quantity.
–
All operations assume a 2's complement representation.
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Ms Vincy Joseph Advanced Microprocessor
•
Unsigned Integer (Word): An unsigned 16-bit quantity.
•
Unsigned Long Integer (Double Word): An unsigned 32-bit quantity.
•
Signed Quad Word: A signed 64-bit quantity.
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Unsigned Quad Word: An unsigned 64-bit quantity.
•
Offset: A 16- or 32-bit offset only quantity which indirectly references another memory location.
•
Pointer: A full pointer which consists of a 16-bit segment selector and either a 16- or 32bit offset.
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Ms Vincy Joseph Advanced Microprocessor TE CMPNA/B
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Char: A byte representation of an ASCII Alphanumeric or control character.
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String: A contiguous sequence of bytes, words or dwords. A string may contain between
1 byte and 4 GB.
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BCD:
A byte (unpacked) representation of decimal digits 0±9.
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Packed BCD: A byte (packed) representation of two decimal digits 0±9 storing one digit in each nibble.
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When 80386 DX is coupled with 387 Numeric Coprocessor then the following common floating point types are supported.
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Floating Point: A signed 32-, 64-, or 80-bit real number representation.
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