IMAPS Global Business Council
Roadmap Process
“The Road Ahead”
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The GBC Roadmap Team
• This Roadmap Process presentation was prepared
by these members of the IMAPS Global Business
Council & National Technology Council:
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Steve Adamson (sadamson@asymtek.com)
Justin Blount (Justin.M.Blount@usa.dupont.com)
Laurie Roth (lroth@kns.com)
Lee Smith (lsmit@amkor.com)
Andy Strandjord (andrew.strandjord@flipchip.com)
Jie Xue (jixue@cisco.com)
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Topics
• Where does IMAPS fit in with the ITRS and iNEMI
Roadmaps?
• What is the ITRS Roadmap and how does it work?
• What is the iNEMI Roadmap and how does it work?
• How does IMAPS interact with this Roadmap Process?
• Why IMAPS should be involved.
• IMAPS Areas of Focus.
• If you are already familiar with the ITRS & iNEMI Roadmap
Process, skip to slide 19
• The Roadmaps:
– ITRS
– iNEMI
• Summary IMAPS Areas of Focus.
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ITRS & iNEMI Packaging Roadmaps Intersect
IMAPS addresses the Semiconductor Packaging needs of this space.
iNEMI
Market Requirements
Tech Requirements
ITRS
Chip Level
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System Level
What is the ITRS?
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The International Technology Roadmap for Semiconductors (ITRS) is an
assessment of semiconductor technology requirements.
The objective of the ITRS is to ensure advancements in the performance of
integrated circuits.
This assessment, called roadmapping, is a cooperative effort of global industry
manufacturers and suppliers, government organizations, consortia, and
universities.
The ITRS identifies the technological challenges and needs facing the
semiconductor industry over the next 15 years.
It is sponsored by the European Semiconductor Industry Association (ESIA),
the Japan Electronics and Information Technology Industries Association
(JEITA), the Korean Semiconductor Industry Association (KSIA), the
Semiconductor Industry Association (SIA), and Taiwan Semiconductor
Industry Association (TSIA).
SEMATECH is the global communication center for this activity. The ITRS team
at SEMATECH also coordinates the USA region events.
http://public.itrs.net/
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ITRS Technology Working Groups
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The ITRS process encourages discussion and debate throughout the community about the
requirements for success.
The key factor in the success of the Roadmap is obtaining consensus on industry drivers,
requirements, and technology timelines.
The Technology Working Groups are the organizations that "build" the roadmaps.
These representatives assess the state of technology and identify areas that may provide solutions.
The TWG members also indicate opportunities for new research and innovation.
These groups are made up of volunteer technology experts from chip manufactures, supplier
companies, universities and academia, technology labs, and semiconductor technology consortia.
The Technology Working Groups, also known as TWGs, are comprised of the technical disciplines of
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System Drivers
Design
Test and Test Equipment
Process Integration, Devices, and Structures
RF and Analog/Mixed-signal Technologies for Wireless Communications
Emerging Research Devices and Materials
Front End Processes
Lithography
Interconnect
Factory Integration
Assembly and Packaging – This is the area where IMAPS will focus.
Environment, Safety, and Health
Yield Enhancement
Metrology
Modeling and Simulation.
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Example of ITRS Short Term Challenges
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iNEMI has strong industry support.
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iNEMI Roadmap Methodology
• iNEMI focusses on top level industry segments via their Product Emulator
Groups.
• In addition, they address technology areas via their different Technology
Working Groups.
• A “cross-cut” matrix ensures feedback between the various groups.
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iNEMI Technology Working Groups
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Business Processes/Technologies:
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Design Technologies:
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Environmentally Conscious Electronics
Modeling, Simulation & Design Tools
Thermal Management
Manufacturing Technologies:
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Product Lifecycle Information
Management
Board Assembly
Test, Inspection & Measurement
Final Assembly
Component Subsystem
Technologies:
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Passive Components
RF Components & Subsystems
Packaging – This is one of the areas
where IMAPS will focus.
Semiconductor Technology
Organic Substrates
Mass Data Storage
Connectors
Energy Storage Systems
Optoelectronics
Sensors
Organic and Printed Electronics
Ceramic Substrates – IMAPS also
contributes to this TWG.
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iNEMI Cross-cut Matrix
A “cross-cut” matrix ensures feedback between the various groups.
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Technical Working Group
Semiconductor Technology
Organic & Printed Electronics (New)
Environmentally Conscious Electronics
Final Assembly
Interconnect Substrates (Organic)
Mass Data Storage
Modeling, Simulation & Design Tools
Optoelectronics
Packaging
RF Components & Subsystems
Test, Inspection and Measurements
Thermal Management
Board Assembly
Passive Components
Energy Storage Systems
Interconnect Substrates (Ceramic)
Product Lifecycle Information Management
Connectors
Sensors
Office / Large Business / Communication
Systems
Portable / Consumer
Automotive
Aerospace/Defense
Medical
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Example of iNEMI short term challenges
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Update calendar for ITRS / iNEMI
• 2006 ITRS Roadmap release scheduled for December 4, 2006.
• 2007 iNEMI Roadmap release scheduled for February 2007 at APEX,
Los Angeles.
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Why IMAPS should be involved.
• ITRS focuses mainly on “front end” wafer fab areas, with a chapter on
Semiconductor Assembly & Packaging.
• iNEMI focuses mainly on “board level” assembly, with a chapter on
Semiconductor Assembly & Packaging.
• ITRS/iNEMI are working together to align their Semiconductor Assembly
& Packaging Roadmaps.
– Many of the same people are on both teams.
– Some IMAPS members are also on both teams.
• IMAPS’ focus is on Semiconductor Assembly & Packaging.
• It’s a natural fit to take the output of the ITRS/iNEMI Semiconductor
Assembly & Packaging Roadmaps and use that output to direct IMAPS’
activities towards solving gaps in the roadmap.
• IMAPS’ corporate members will benefit by developing real industry
solutions for real industry challenges.
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Global Semiconductor Packaging Materials Outlook
Market Size for Materials = Market Opportunities for IMAPS members.
Millions of U.S. Dollars
Organic Substrates
Leadframes
Bonding Wire
Mold Compounds
Die Attach Materials
Thermal Interface Materials
Solder Balls
Underfill Materials
Liquid Encapsulants
Wafer Level Package Dielectrics
TOTAL
Estimate
2005
$ 4,545
$ 3,010
$ 1,809
$ 1,569
$
463
$
284
$
137
$
97
$
99
$
8
$ 12,020
Forecast
2006
$ 5,682
$ 3,045
$ 2,057
$ 1,710
$
489
$
326
$
173
$
122
$
105
$
15
$ 13,724
2007
$ 6,720
$ 3,061
$ 2,193
$ 1,732
$
526
$
374
$
216
$
167
$
110
$
32
$ 15,131
Source: SEMI Industry Research and Statistics and TechSearch International, November 2005
This forecast was supplied courtesy of SEMI & Techsearch International.
The full report is available from SEMI’s web catalog at www.semi.org .
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2008
$ 8,287
$ 3,041
$ 2,327
$ 1,736
$
564
$
432
$
255
$
221
$
114
$
51
$ 17,028
2009
$ 8,986
$ 2,965
$ 2,373
$ 1,786
$
583
$
495
$
322
$
266
$
117
$
68
$ 17,962
2010
$ 10,108
$ 2,950
$ 2,518
$ 1,842
$
609
$
526
$
402
$
331
$
120
$
88
$ 19,495
Launched “The Road Ahead” in Advancing Microelectronics 4/06
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Roll-out plan for IMAPS to address roadmaps
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Form a GBC Roadmap Team.- DONE
GBC Roadmap Team creates a roadmap template (“red brick”) and identifies current gaps
on the existing roadmaps. - DONE
GBC Roadmap Team communicates those gaps to the NTC.
GBC and NTC structure future IMAPS events to focus on those gaps – ongoing.
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Dave Saums to give short presentation at LED & Thermal ATWs in September 2006.
Meantime, GBC/NTC to support ITRS/iNEMI updates with input & communicate back to
IMAPS issues/trends.
– Use IMAPS members on the ITRS/iNEMI roadmap TWGs to facilitate communication:
Laurie Roth, Howard Imhof....and other volunteers.
"Red Brick" template
2006
2007
2008
etc
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Manufacturing solutions exist and are being optimized.
Manufacturing solutions are know.
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Interim solutions are known.
Manufacturable solutions are NOT known.
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Recommended Areas of Focus for IMAPS Members
• Develop Feasible Embedded Components.
• Develop Enhanced Materials to Enable Wafer Level Packaging.
• Bring Solutions to Resolve Thermal Management Issues.
• Develop New Materials to Reduce System Cost While
Delivering the Necessary Performance.
• Close the Gap Between Chip and Substrate Interconnect
Density.
• Resolve the issues low K and Cu bring to Packaging.
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The Roadmaps
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The complete chapter can be downloaded from the ITRS website:
http://www.itrs.net/Common/2005ITRS/AP2005.pdf
The following slides contain key excerpts.
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ITRS 2005 Semiconductor Packaging Roadmap Table of Contents
All of these topics – and those on the next slide – are comprehensively covered in the ITRS Roadmap.
This presentation will focus on the key challenges only.
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Chapter Scope
Difficult Challenges
Technology Requirements
Single Chip Packages
High Pin-Count Packages
Wafer Level Packaging
System in a Package (Multi-chip
Packages, 3D Packaging)
Flexible Substrates and Interconnect
Optoelectronic Packaging
RF Packaging
MEMS
Medical and Bio Chip Packaging
Biocompatibility
Bio Packaging Reliability
Integrated Circuit
Manufacturing
Cost
Reliability
Package and Interconnect
Characterization and Simulation
Simulation
Reliability Testing
Soft Errors
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Packaging Materials Requirements
New Materials
Embedded and Integrated Passives
Assembly and Packaging Infrastructure Challenges
Electrical Design Requirements
Cross Talk
Power Distribution and Power Subsystem
Thermo-mechanical Challenges in Electronic Packaging
Mechanical Challenges
Mechanical Modeling and Simulation and Validation
Thermal Modeling and Simulation and Validation
Equipment Requirements for Emerging Package Types
Potential Solutions
Wafer Level Packaging
Chip to Next Level Interconnect
Package to Board Interconnect
Fine Pitch Ball Grid Array/CSP Packages
Socketed Parts
Embedded and Integrated Passives
Package Substrates
Build-Up and Coreless Substrates
Rigid Substrate Technology
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ITRS 2005 Semiconductor Packaging Roadmap Table of Contents
continued
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System in Package (SiP) – System Level Integration
Types/Categories of SiP’s
Side by Side Placement (Horizontal Packages)
Stacked Structures
Package-on-Package (POP), Package-in-Package (PiP)
Stacked Die Packages
Chip to Chip/Wafer Structure
Embedded Structures
Technologies for SiP
Wafer level SiP and 3 D Integration Technologies
Technologies for Embedded Devices
Challenges for SiP
Thermal management
System in Package Outlook
Wafer Thinning
Glossary of Terms
Cross-Cut ITWG Issues
Design
Factory Integration
Die Traceability Crosscut with Factory Integration
Interconnect
RF/AMS Wireless
Environment, Safety and Health
Modeling and Simulation
Metrology
Test
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ITRS: Single Chip Package
• Incremental improvements in traditional assembly technologies will not
be sufficient to meet market requirements.
• The substrate dominates the cost of single chip packaging.
• Cost per pin has been trending up, instead of down.
• Operating temperatures are a problem in harsh environments.
• Higher frequency chip-to-board speeds for peripheral buses.
Table 94a Single-chip Packages Technology Requirements—Near-term Years
Year of Production
2005
2006
2007
2008
2009
2010
Cost per Pin Minimum for Contract Assembly [1,2] (Cents/Pin)
Low-cost, hand held and memory
.27–.50
.26–.49
.25–.48
.24–.47
.23–.46
.22–.45
Cost-performance
.68–1.17
66–1.11
.64–1.05
.63–1.00
.62–.96
0.61–.94
High-performance
1.78
1.74
1.71
1.68
1.64
1.61
Harsh
0.29–2.61 0.26–2.34 0.25–2.11 0.23–2.00 0.22–1.90 0.22–1.54
Maximum Junction Temperature
Harsh
Operating Temperature Extreme: Ambient (°C)
Harsh
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175
-40 to 150
-40 to 150
-40 to 150
-40 to 150
2012
2013
.21–.43
.60–.92
1.58
.21-1.46
.20–.42
0.58–.90
1.55
0.20–1.38
.20–.41
0.57–.89
1.51
0.20–1.31
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220
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220
-40 to 150 -40 to 200
-40 to 200
200
2011
-40 to 200 -40 to 200
Table 94b Single-chip Packages Technology Requirements—Long-term Years
Year of Production
High-performance (for differential-pair point-to-point nets)
2014
2015
2016
2017
2018
2019
2020
23282
29102
36378
45472
56840
71051
88813
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Maximum Junction Temperature
Harsh
Operating Temperature Extreme: Ambient (°C)
Harsh
-40 to 200 -40 to 200 -40 to 200 -40 to 200 -40 to 200 -40 to 200 -40 to 200
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ITRS: High Pin-Count Packages
• Package pin count grows as higher frequency and higher
power density demand more power and ground pins.
• Substrate technology requires micro-vias, blind & buried
vias, stacked vias and tighter lines and spacing.
• Substrate technology advances lead to significant cost
increases for design/test and a reduced supplier base.
• System-in-Package will become more important to reduce
the need for high density interconnects in the package
substrate and the PCB.
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ITRS: Chip-to-Package Substrate
Development work is required for finer pitch in-line wire bond & area array flip chip.
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ITRS: Package Substrate Physical Properties – Near Term
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ITRS: Package Substrate Physical Properties – Long Term
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ITRS: System-in-Package - definitions
• SiP enables reduction in size, weight, cost & power.
– System-on-Chip can address size, weight & power, but at cost,
design & test premiums.
• SiP integrates multiple functions/devices in a single package.
– Can integrate different elements such as MEMS, opto, bio....
• Includes 3D “stacked die” packaging.
• Requires Known Good Die.
SoC and SiP Comparison for Cost per
Function and Time to Market vs. Complexity
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ITRS: System-in-Package Requirements
The number of stacked die and the number of die in a SiP are challenges.
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ITRS: Thinned Wafers
Long term challenge for extreme thin packages.
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ITRS: Wafer Level Packaging
• Near term challenges:
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I/O pitch between 150 µm - 250 µm >100 I/O
Solder joint reliability
Wafer thinning and handling technologies
Compact ESD structures
TCE mismatch compensation for large die
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ITRS: Flexible Substrates
• Near term challenges:
– Conformal low cost organic substrates
– Small and thin die assembly
– Handling in low cost operation
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ITRS: Interconnect
It is very challenging to maintain packaging reliability with strong chip-to-package
interaction resulting from new materials, new processes, and new interconnect
features at the Si level.
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ITRS: Interconnect (cont’d)
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ITRS: Optoelectronic Packaging
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Package Sealing
– Hermetic sealing to protect the optical devices - TO header & butterfly packaging.
– Non-hermetically sealed organic packaging for cost sensitive applications.
Alignment
– < 0.5 µm alignment between single mode fiber & optical device for high data rate
applications.
– 5 to 10 µm alignment accuracy for cost sensitive applications, using relatively large
diameter polymer optical fiber (POF)
– Adhesive to assure alignment through succeeding high temperature processes &
product usage life.
Materials
– POF material improvement in attenuation reduction and data rate increase is required.
– Material development for poly-clad-silica (PCS) fiber.
– Optically clear molding compound or clear glob tops for optical windows.
Vertical integration to include more functionality in a package.
– Wafer-level-packaging (WLP) process to integrate lenses or other microopticalelectro-mechanical system (MOEMS) devices, and to provide environmental
protection for a VCSEL wafer.
– Some micro-optical components, e.g. polymer waveguides and beam reflectors, may
be embedded in the SiP substrate.
– A BGA based SiP may house optical connectors, laser diodes, photodetectors, CMOS
IC containing receivers/drivers and multiplexer/demultiplexer, plus RF connectors, and
decoupling capacitors.
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ITRS: RF Packaging
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Many of the technology challenges for RF packaging arise from the fact that the IC
packaging engineering practice, technology knowledge base, and manufacturing
infrastructures have been based upon digital IC packaging developed in the last forty
odd years.
Issues
– The inductance characteristics associated with bonding wires and leaded
packages, and effect of molding compound materials limit the RF performance.
– RF package modeling tools and materials properties database for package
design and device-package co-design for the broad spectrum of RF market
applications.
– Improvements in materials properties—molding compounds, underfills,
substrates are required.
– Being able to embed passive components in LTCC.
– To meet the low cost challenges, embedded inductance and capacitance
components and networks in organic packaging for RF applications must be
diligently pursued.
– Tools to enable device package co-design in SIP packages will be very
important.
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ITRS: MEMS
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ITRS: Medical & Bio Chip Packaging
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BIOCOMPATIBILITY
– No interaction with body tissues and fluids.
– No inflammatory reactions.
– No toxicity to bio-organisms.
– No outgassing or other decay products that may be harmful to bio-organisms.
– Must be chemically inert to various concentrations of bio-reagents including ethanol.
– May include high flow rates with significant back pressure.
BIO PACKAGING RELIABILITY
– Major concerns are patient safety and risk mitigation.
– For life-sustaining devices, component failure rate as low as 100 ppm, few ppm critical failure rate.
– Challenge to capture low occurrence failures in reliability testing.
– EMI is a major concern.
– Pressure requirements: in a barometric pressure chamber or while scuba diving.
– Defibrillation devices could generate significant localized heating in the high voltage charging circuit
when delivering therapy, challenging the package substrate and PCB.
MANUFACTURING
– In accordance with regulatory requirements for medical devices
– Requirements for control of the manufacturing environment, labeling of the packages, and
documentation.
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ITRS: Cost
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Today packaging costs often exceed die fabrication costs.
Leadfree solders.
Low K & High K dielectrics.
Higher processing temperatures.
Wider range of environmental temperatures.
More efficient thermal management needed.
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ITRS: Reliability & Simulation
New failure modes caused by new materials needed to meet environmental and performance
requirements, result in significant challenges in field reliability prediction based on
accelerated lab testing for broad product application field requirements.
• The introduction of the new materials and structures to meet
environmental, heat and speed requirements are posing new reliability
challenges.
• New technology will be required to meet the reliability goals including:
1. New reliability tests such as drop tests for mobile products.
2. Correlation between field- and laboratory testing.
3. Improved methods for failure detection and analysis (e.g., X-ray,
acoustic, nano-deformation and localized residual stress
measurement.)
4. Materials and interface characterization. Interfacial delamination will
continue to be a critical reliability hazard that is worsened by the
trends to larger chips, new materials and increased layer count.
More layers require the understanding of more interfaces.
5. Simulation and modeling for life time prediction (e.g., multi-field
coupling, structure-property correlation, ab-initio methods, modular
and parametric approaches).
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ITRS: Packaging Materials
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ITRS: Infrastructure
• Electrical design
– Cross talk
– Power distribution & power subsystem
• Thermo-mechanical
– Modeling & Simulation
• Equipment
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www.inemi.org
•The iNEMI Roadmap is only available for download to TWG
members or on-line purchase.
•The following slides contain key excerpts from the 2007
Roadmap Update-in-progess.
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Recommended Areas of Focus for IMAPS Members
Summary
• Develop Feasible Embedded Components.
• Develop Enhanced Materials to Enable Wafer Level Packaging.
• Bring Solutions to Resolve Thermal Management Issues.
• Develop New Materials to Reduce System Cost While
Delivering the Necessary Performance.
• Close the Gap Between Chip and Substrate Interconnect
Density.
• Resolve the issues low K and Cu bring to Packaging.
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Back Up
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ITRS: Difficult Challenges ≥ 32 nm – Near Term
The ITRS Roadmap segments issues into those that are Near Term & affect Wafer
Nodes ≥ 32 nm and those that are Long Term & affect Wafer Nodes <32 nm.
Impact of new materials
Wafer Level Packaging
BEOL materials including Cu/low κ
Direct wirebond and bump to Cu or improved barrier systems bondable pads
Bump and underfill technology to assure low-κ dielectric integrity including lead
free solder bump system
Improved fracture toughness of dielectric materials
Interfacial adhesion
Reliability of first level interconnect with low κ
Mechanisms to measure the critical properties need to be developed
Probing over copper/low κ
Singulation technology for circuits incorporating ultra low κ dielectrics
I/O pitch between 150 µm and 250 µm greater than 100 I/O
Solder joint reliability
Wafer thinning and handling technologies
Compact ESD structures (this applies to other package types as well)
TCE mismatch compensation for large die
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ITRS: Difficult Challenges ≥ 32 nm – Near Term
Coordinated Design Tools and Simulators to
address Chip, Package, and Substrate
Codesign
Embedded Components
Thinned die packaging
Mix signal co-design and simulation environment
Rapid turn around modeling and simulation
Integrated analysis tools for transient thermal analysis and integrated thermal
mechanical analysis
Electrical (power disturbs, EMI, signal and power integrity associated with higher
frequency/current and lower voltage switching)
In package decoupling
System level co-design
EDA for “native” area array is required to meet the Roadmap projections
Models for reliability prediction
Low cost embedded passives: R, L, C
Embedded active devices at both wafer and substrate level
Wafer level embedded components
Wafer/die handling for thin die
Compatibility of different carrier materials (organics, silicon, ceramics, glass,
laminate core)
Reliability
Testability
Thin die for embedded active devices
Electrical and optical interface integration
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ITRS: Difficult Challenges ≥ 32 nm – Near Term
Close gap between chip and substrate –
Improved Organic Substrates
High Current Density Packages
Flexible System Packaging
Increased wireability at low cost
Improved impedance control and lower dielectric loss to support higher
frequency applications
Improved planarity and low warpage at higher process temperatures
Low-moisture absorption
Increased via density in substrate core
Alternative plating finish to improve reliability
Tg compatible with Pb free solder processing (including rework @260C)
Electromigration
Thermal/mechanical reliability modeling.
Whisker growth
Thermal dissipation
Conformal low cost organic substrates
Small and thin die assembly
Handling in low cost operation
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ITRS: Difficult Challenges ≥ 32 nm – Near Term
3D Packaging
Fine Pitch Packages
Thermal management
Co-Design and simulation tools
Wafer to wafer bonding
Through wafer Via structure and via fill process
Bumpless interconnect architecture
Tighter tolerances for fine pitch BGA
Minimizing kerf loss in singulation for small outline packages
High temperature warpage for fine pitch BGA
Reliability to meet drop test requirements for mobile electronics
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ITRS: Difficult Challenges < 32 nm – Long Term
Package Cost does not follow the Die Cost Reduction Curve
Small Die with High Pad Count and/or High Power Density
High Frequency Die
System-level Design Capabilityfor Integrated Chips,
Passives, and Substrates
Emerging Device Types (Organic, Nanostructures,
Biological) that require New Packaging Technologies
Margin in packaging is inadequate to support investment required to reduce cost
Increased device complexity requires higher cost packaging solutions
These devices may exceed the capabilities of current assembly and packaging
technology requiring new solder/UBM with:
Improved current density capabilities
Higher operating temperature
Substrate wiring density to support >20 lines/mm
Lower loss dielectrics—skin effect above 10 GHz
“Hot spot” thermal management
Partitioning of system designs and manufacturing across numerous companies will
make optimization for performance, reliability, and cost of complex systems very
difficult.
Complex standards for information types and management of information quality
along with a structure for moving this information will be quality along with a structure
for moving this information will be required.
Embedded passives may be integrated into the “bumps” as well as substrates.
Organic device packaging requirements not yet define (will chips grow their own
packages) Biological packaging will require new interface types
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