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Area Efficient Double Edge Triggered Double Tail Comparator
Greeshma A G 1, Sajithra S I 2 and Surya kumari V 3
1 Post
2
Graduate Scholar, Department of ECE, PPG Institute of Technology, Coimbatore, Thamilnadu, India.
Post Graduate Scholar, Department of ECE, PPG Institute of Technology, Coimbatore, Thamilnadu, India.
3Assistant Professor, Department of ECE, PPG Institute of Technology, Coimbatore, Thamilnadu, India.
ag.greeshma88@gmail.com
sajithra.25@gmail.com
suryappgit@yahoo.com
Abstract— Comparator is one of the main building blocks in
most analog-to-digital converters. Many high speed analog-todigital converters, such as flash ADCs, require high-speed,
low power comparators with small chip area. In low power,
area efficient, and high speed analog-to-digital converters we
need dynamic regenerative comparators to increase speed and
power efficiency. In this paper, a new dynamic comparator is
proposed, where the circuit of a low voltage low power double
tail comparator is modified for area efficient and double edge
triggered operation. The simulated data presented is obtained
using TANNER EDA tool with 180 nm technology. It is shown
that in the proposed dynamic comparator both the power
consumption delay time and are significantly reduced.
Keywords— Double edge triggering, double tail comparator,
dynamic regenerative comparator, high speed analog-todigital converters.
I. INTRODUCTION
Developing new circuit is preferable for low voltage
operation, especially if they do not increase the circuit
complexity. The circuit of a low voltage low power double
tail comparator [1] is modified for area efficient and double
edge triggered operation while delay and power
consumption. The structure of double tail dynamic
comparator first proposed based on designing a separate
input and cross coupled stage. This separation helps in fast
operation over a wide common mode and supply voltage
range.
The comparator compares the voltages that appear at their
inputs and outputs a voltage representing the sign of the net
difference between them. The comparator is a circuit that
compares an analog signal with another analog signal or
reference and outputs a binary signal based on the
comparison. If the +, INP, the input of the comparator is at
a greater potential than the -, INN, input, the output of the
comparator is a logic 1 and vice versa. Comparators are
important elements in modern mixed signal systems. Speed
and resolution are two important features which are
required for high speed applications such as on-chip high
frequency signal testing, data links, sense amplifiers and
analog-to-digital converters. On-chip testing of high
frequency pseudo random binary sequences (PRBS)
requires a high speed comparator at the electrical interface
stage.
A clocked comparator generally consists of two stages. In
that first stage is to interface the input signals. The second
(regenerative) stage consists of two cross coupled inverters,
where each input is connected to the output of the other. In
a cMOS based latch, the regenerative stage and its
following stages consume low static power since the power
ground path is switched off either by an nMOS or a pMOS
transistor.
In many applications comparator speed, power dissipation
and number of transistors are more important. If
comparator speed is a priority, the regenerative stage could
be designed to start its operation from midway between
power supply and ground, for example, pre-amplifier based
clocked comparator.
However, the static power consumption is relatively high.
If comparator was designed with priority given to power
reduction, then number of transistors increases thereby
reducing the speed, for example double tail latched
comparator.
Comparator design largely depends on the target
application. However, an input-referred latch offset voltage
(hence offset voltage), resulting from the device
mismatches such as threshold voltage Vth, current factor β
(=μCoxW/L) and parasitic node capacitance and output load
International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 4, April 2013)
capacitance mismatches, limits the accuracy of such
comparators.
regenerative comparators have wide applications in
many high speed ADCs because they can make fast
decisions due to the strong positive feedback in the
regenerative latch. Here existing low voltage low
power double tail comparator is analyzed first and
then a modified comparator is proposed.
The rest of this paper is organized as follows. Section
II investigates the operation of the existing
comparator. The proposed comparator is presented in
Section III. Simulation results are addressed in
Section IV, followed by conclusions in Section V.
II. EXISTING COMPARATOR
Fig. 2 Low Voltage Low Power Double Tail Comparator.
The operation of the comparator is as follows. During
reset phase (CLK = 0, Mtail1 and Mtail2 are off), M3 and
M4 pulls both fn and fp nodes to VDD, hence transistor
Mc1 and Mc2 are cut off. Intermediate stage transistors,
MR1 and MR2, reset both latch outputs to ground.
Fig. 1 Main Idea of Low Voltage Low Power Double Tail Comparator.
Almost all comparators are based upon two
symmetric sub circuits. Clocked comparators are
often called Dynamic Comparators. Regeneration is
obtained by symmetrically cross coupling across axis
of symmetry from an output to an input. Clocked
During decision-making phase (CLK = VDD, Mtail1,
and Mtail2 are on), transistors M3 and M4 turn off.
Furthermore, at the beginning of this phase, the
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Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 4, April 2013)
III. PROPOSED DOUBLE TAIL COMPARATOR
control transistors are still off (since fn and fp are
about VDD). Thus, fn and fp start to drop with
different rates according to the input voltages.
Suppose VINP > VINN, thus fn drops faster than fp,
(since M2 provides more current than M1). As long as
fn continues falling, the corresponding pMOS control
transistor (Mc1 in this case) starts to turn on, pulling fp
node back to the VDD; so another control transistor
(Mc2) remains off, allowing fn to be discharged
completely. In the proposed structure as soon as the
comparator detects that for instance node fn
discharges faster, a pMOS transistor (Mc1) turns on,
pulling the other node fp back to the VDD. Therefore
by the time passing, the difference between fn and fp
(∆Vfn/fp) increases in an exponential manner, leading
to the reduction of latch regeneration time.
Fig. 3 Proposed Double Tail Comparator.
Despite the effectiveness of this idea, one of the
points which should be considered is that in this
circuit, when one of the control transistors (e.g., Mc1)
turns on, a current from VDD is drawn to the ground
via input and tail transistor (e.g., Mc1, M1, and Mtail1),
resulting in static power consumption. To overcome
this issue, two nMOS switches are used below the
input transistors [Msw1 and Msw2, as shown in Fig. 2].
At the beginning of the decision making phase, due to
the fact that both fn and fp nodes have been precharged to VDD(during the reset phase), both switches
are closed and fn and fp start to drop with different
discharging rates. As soon as the comparator detects
that one of the fn/fp nodes is discharging faster,
control transistors will act in a way to increase their
voltage difference. Suppose that fp is pulling up to the
VDD and fn should be discharged completely, hence
the switch in the charging path of fp will be opened
(in order to prevent any current drawn from VDD) but
the other switch connected to fn will be closed to
allow the complete discharge of fn node. In other
words, the operation of the control transistors with the
switches emulates the operation of the latch.
In the proposed comparator circuit complexity is
reduced. Number of transistors is reduced from 16 to
12. The new comparator is double edge triggered. It
works for both the positive and negative edges of
clock.
Working principle of the proposed comparator is
same as that of low voltage low power comparator.
When clock is high M1 and M7 are off and M6 and
M8 are on. When clock is low M6 and M8 are off and
M1 and M7 are on. An input dependent differential
voltage ∆Vfn(p) will build up depending on change in
input values. The intermediate stage formed by MR1
and MR2 passes ∆Vfn(p) to the cross coupled
inverters and also provides a good shielding between
input and output. Depending on the difference in
inputs we will get the output.
IV. SIMULATION RESULTS AND COMPARISON
The proposed circuit was simulated using Tanner
EDA tool with 180nm technology. The supply voltage
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International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 4, April 2013)
used in simulation is 1.8 volt. From table 1 it is
visible that average power consumption, EDP and
PDP of proposed comparator reduced.
TABLE I
PERFOMANCE COMPARISON
Performance
Parameter
Existing
Comparator
Proposed
Comparator
Average Power
1.77×10-4 W
8.37×10-8 W
Maximum Power
2.27×10-3 W
6.06×10-5W
Minimum Power
1.77×10-10
W
8.46×10-11 W
Static Current
1.26 ×10-3A
3.37 ×10-5A
Power Delay Product
4.54×10-8 Ws
12.12×10-10 Ws
Energy Delay Product
9.08×10-13 Ws2
24.24×10-15 Ws2
Area
704µm2
528µm2
Fig. 5 Power Result of Proposed Comparator.
V. CONCLUSIONS
In this paper, an analysis for clocked dynamic comparators
is presented. One structure of double-tail dynamic
comparators was analysed. Also, based on analyses, a new
dynamic comparator with low-voltage low-power
capability was proposed in order to improve the
performance of the comparator. Simulation results in 0.18μm CMOS technology confirmed that the delay and power
consumption of the proposed comparator is reduced to a
great extent in comparison with the existing double-tail
comparator.
Fig. 4 shows the simulation result of the proposed
comparator and the power result of the proposed
comparator is shown in Fig. 5.
REFERENCES
[1] Samaneh Babayan-mashhadi, And Reza Lotfi, “Analysis And
Design Of A Low-voltage Low-power Double-tail Comparator”,
IEEE Trans. on Very Large Scale Integration (Vlsi) Systems,
2013.
[2] B. Goll and H. Zimmermann, “A comparator with reduced
delay time in 65-nm CMOS for supply voltages down to 0.65,”
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 11, pp.
810–814, Nov. 2009.
[3] S. U. Ay, “A sub-1 volt 10-bit supply boosted SAR ADC
design in standard CMOS,” Int. J. Analog Integr. Circuits Signal
Process., vol. 66, no. 2, pp. 213–221, Feb. 2011.
Fig. 4 Simulation Result of Proposed Comparator.
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International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 4, April 2013)
[14] S. Babayan-Mashhadi and R. Lotfi, “An offset cancellation
technique for comparators using body-voltage trimming,” Int. J.
Analog Integr. Circuits Signal Process., vol. 73, no. 3, pp. 673–
682, Dec. 2012.
[4] A. Mesgarani, M. N. Alam, F. Z. Nelson, and S. U. Ay,
“Supply boosting technique for designing very low-voltage
mixed-signal circuits in standard CMOS,” in Proc. IEEE Int.
Midwest Symp. Circuits Syst. Dig. Tech. Papers, Aug. 2010, pp.
893–896.
[15] J. He, S. Zhan, D. Chen, and R. J. Geiger, “Analyses of static
and dynamic random offset voltages in dynamic comparators,”
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 5, pp. 911–
919, May 2009.
[5] B. J. Blalock, “Body-driving as a Low-Voltage Analog Design
Technique for CMOS technology,” in Proc. IEEE Southwest
Symp. Mixed-Signal Design, Feb. 2000, pp. 113–118.
[6] M. Maymandi-Nejad and M. Sachdev, “1-bit quantiser with
rail to railinput range for sub-1V ∆ modulators,” IEEE Electron.
Lett., vol. 39, no. 12, pp. 894–895, Jan. 2003.
[16] J. Kim, B. S. Leibowits, J. Ren, and C. J. Madden,
“Simulation and analysis of random decision errors in clocked
comparators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56,
no. 8, pp. 1844–1857, Aug. 2009.
[7] Y. Okaniwa, H. Tamura, M. Kibune, D. Yamazaki, T.-S.
Cheung, J. Ogawa, N. Tzartzanis, W. W. Walker, and T. Kuroda,
“A 40Gb/s CMOS clocked comparator with bandwidth
modulation technique,” IEEE J. Solid-State Circuits, vol. 40, no.
8, pp. 1680–1687, Aug. 2005.
[17] P. M. Figueiredo and J. C. Vital, “Kickback noise reduction
technique for CMOS latched comapartors,” IEEE Trans. Circuits
Syst. II, Exp. Briefs, vol. 53, no. 7, pp. 541–545, Jul. 2006.
[18] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and
speed optimization of a latch-type voltage sense amplifier,” IEEE
J. Solid-State Circuits, vol. 39, no. 7, pp. 1148–1158, Jul. 2004.
[8] B. Goll and H. Zimmermann, “A 0.12 μm CMOS comparator
requiring 0.5V at 600MHz and 1.5V at 6 GHz,” in Proc. IEEE Int.
Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2007, pp. 316–
317.
[19] D. Johns and K. Martin, Analog Integrated Circuit Design,
New York,
[9] B. Goll and H. Zimmermann, “A 65nm CMOS comparator
with modified latch to achieve 7GHz/1.3mW at 1.2V and
700MHz/47μW at 0.6V,” in Proc. IEEE Int. Solid-State Circuits
Conf. Dig. Tech. Papers, Feb. 2009, pp. 328–329.
USA: Wiley, 1997.
AUTHORS PROFILE
Greeshma A G received the B.Tech degree in
Electronics and Communication Engineering
(ECE) from SNMIMT Engineering College,
Maliankara, India in 2010. She is currently
pursuing the Master Degree from PPG Institute
of Technology, Coimbatore, Anna University,
Chennai. Her current research interest includes
low power, high speed and area efficient design of comparators
for low supply voltages.
[10] B. Goll and H. Zimmermann, “Low-power 600MHz
comparator for 0.5 V supply voltage in 0.12 μm CMOS,” IEEE
Electron. Lett., vol. 43, no. 7, pp. 388–390, Mar. 2007.
[11] D. Shinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B.
Nauta, “A double-tail latch-type voltage sense amplifier with 18ps
Setup+Hold time,” in Proc. IEEE Int. Solid-State Circuits Conf.,
Dig. Tech. Papers, Feb. 2007, pp. 314–315.
[12] P. Nuzzo, F. D. Bernardinis, P. Terreni, and G. Van der Plas,
“Noise analysis of regenerative comparators for reconfigurable
ADC architectures,” IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 55, no. 6, pp. 1441–1454, Jul. 2008.
Sajithra. S. I. completed B.E in Electronics and Communication
Engineering from Vins Christian College of Engineering under
Anna University in 2012. She is currently pursuing the Master
Degree from PPG Institute of Technology, Coimbatore, Anna
University, Chennai. Her current research interest includes
clinical diagnosis of malignant melanoma.
[13] A. Nikoozadeh and B. Murmann, “An analysis of latched
comparator offset due to load capacitor mismatch,” IEEE Trans.
Circuits Syst. II, Exp. Briefs, vol. 53, no. 12, pp. 1398–1402, Dec.
2006.
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International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 4, April 2013)
Surya kumari . V received her B.E in
Electronics and Communication Engineering
from SNS college of Coimbatore, India in
2010 and Masters Degree in VLSI Design
from Government College of Technology,
Coimbatore India in 2012. She has 1 year 9
months of teaching experience and currently
working as Assistant Professor in the Department of Electronics
and Communication Engineering, PPG Institute of Technology,
Coimbatore, affiliated to Anna University, Chennai, India.
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