The Continued Evolution of
Re-Configurable FPGAs for
Aerospace and Defense
Strategic Applications
Howard Bogrow
Abstract
Present and future aerospace and defense applications continue to demand
ever increasing performance, density, and above all flexibility from FPGAs. The
Virtex families of re-configurable FPGAs provide the technology to meet these
demands. Various members of these families are currently available in both
COTs and SMD formats, as well as in radiation tolerant versions. Xilinx is also
fully supporting a recently announced software tool that automates the
implementation of TMR (Triple Modular Redundancy) into members of these
FPGA families for mission critical applications.
Xilinx has received government funding towards the development of a Single
Event Immune Re-configurable FPGA (SIRF) with possibly strategic
performance. This paper will focus on Xilinx currently available Virtex solutions,
while also discussing Xilinx's future development efforts. There will also be
some discussion of the various manufacturing flows utilized by Xilinx to address
the stringent requirements of current and future space missions, as well as the
latest package developments.
Bogrow
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Xilinx Long-Term Commitment to
Aerospace & Defense
1st 90nm Virtex-4 Platform FPGA
04
Rad tolerant Virtex-II Pro
Xilinx on Mars
1st 130nm Virtex-II Pro
02
SEE Consortium formed
1st 150nm Virtex-II Platform FPGA
00
Rad tolerant Virtex & SPROMs
98 Virtex million-gate FPGAs
1st 0.35 & 0.25mm FPGAs
1st rad tolerant devices
QML & ISO9001 certifications 97
95 ISO 9002 certification
91 1st Standard Military Drawing (SMD) released
89 1st device qualified to MIL-STD-883
85 Introduced 1st field programmable gate array (FPGA)
84 Xilinx Founded
1985
1990
1995
2000
Source: Company reports
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2005
Xilinx Technology Roadmap
180 nm
• Leading SIA Roadmap
–
–
Virtex-E
Extended Memory
150nm, 130nm and 90nm
300mm wafers starting with Virtex-II
and Virtex-E
• First 90nm Spartan-3 family in full
production
• First Virtex-4 devices now shipping
150 nm
Virtex-II
130 nm
Virtex-IIPRO
Virtex-4
90 nm
Spartan-3
65 nm
45 nm
1999
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2000
2001
2002
4
2003
2004
2005
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Aerospace and Defense
Virtex Mil Spec Products
Next Generation
Virtex-4
65nm
90nm
Mil-Temp Space Grades
Virtex-IIPRO
Mil-Temp
130nm
Space Grades
150nm
Virtex-II
Mil-Temp Space Grades
180nm
Rad Tolerant
220nm
“Rad by Design” Program
2003
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2004
2005
5
2006
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Aerospace and Defense
Qualifications
Years from
Commercial
Production
Qualification
Closing the Gap with Commercial
4
3
XC3000
XC4000
XC4000E
XQ4000EX
XQ4000XL
Virtex
Virtex-E Virtex-II Virtex-II Pro
Virtex
Virtex-E
XQ4000XL
2
Virtex-4
Virtex-II Virtex-II Pro
Military Qualification
1
RadHard By
Design Program
Virtex-4
Space Qualification
Program Goals
FPGA Family Generations
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Virtex-4 ASMBL™ Columnar
Architecture
• Virtex 4th Generation advanced
FPGA architecture
• Enables “dial-In” resource
allocation mix
– Logic, DSP, BRAM, I/O, MGT,
DCM, PowerPC
• Enabled by Flip-Chip
packaging technology
– I/O columns distributed
throughout the device
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Three Virtex-4 Platforms
LX
FX
SX
Resource
Logic
14-200K LCs
12-140K LCs
23-55K LCs
0.9-6Mb
0.6-10Mb
2.3-5.7Mb
4-12
4-20
4-8
32-96
32-192
128-512
240-960
240-896
320-640
RocketIO
N/A
0-24 Channels
N/A
PowerPC
N/A
1 or 2 Cores
N/A
Ethernet MAC
N/A
2 or 4 Cores
N/A
Memory
DCMs
DSP Slices
SelectIO
Density
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Processor Cores
8
DSP
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Process Technology Advances
• Advanced 90-nm process
• 11-Layer metallization
Drain
Metal
Connection
Source
Metal
Connection
– 10 copper + 1 aluminum
• New Triple-Oxide Structures
– Lower quiescent power
consumption
• Benefits:
–
–
–
–
Best cost
Gate
Highest performance
Source
Channel
Drain
Lowest power
Highest density
• Over 1 million 90 nm FPGAs
shipped
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Dramatic Power Reduction in
Virtex-4
Challenges
- Static power grows with process generations
- Transistor leakage current
- Dynamic power grows with frequency
- P = cv2f
Power
Consumption
Virtex-4 cuts power by 50%
•
•
•
•
•
Lower core voltage
Less capacitance
Up to 10x lower dynamic power with hard IP
•
Bogrow
50%
Measured 40% lower static power with
Triple-Oxide technology
50% lower dynamic power with 90-nm
Frequency
Integration means fewer transistors per function
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Virtex-4 Configuration Features
• Higher configuration speed
– 100MHz Serial & Parallel interface
– 66MHz JTAG interface
•
•
•
•
•
•
•
CCLK available to users
256 bit AES security
Configuration ECC
ICAP and DRP support
Dedicated configuration I/O bank
Enhanced partial reconfiguration
Compatible with previous FPGAs
TCK
TDI
TMS
D[7:0]
TDO
DOUT_BUS
Y
DIN
MODE[2:0]
PROG_B
DONE
RDWR_B
CS_B
INIT
CCLK
• Supports earlier configuration modes
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FPGA Radiation Tolerance
TID Trends vs Product/Technology
• 220nm - XQVR (Virtex)
– 100 krad (Si)
400
350
300
(per 1019.5)
– 60 krad (Si)
TID Krads (Si)
• 350nm - XQ4000XL
250
200
150
100
50
0
• 150nm - XQR2V (Virtex-II)
– 200 krad (Si)
• 130nm – XQR2VP
– 250 krad (Si)
•
90nm (Preliminary)
– 300 krad (Si)
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350
300
250
200
nm
150
100
50
Process trends*:
• Gate oxide continues to thin
• Oxide tunnel currents increase
• Gate stress voltage decreases
*See “CMOS SCALING, DESIGN PRINCIPLES and HARDENING-BYDESIGN METHODOLOGIES” by Ron Lacoe, Aerospace Corp
2003 IEEE NSREC Short Course 2003
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SEE Consortium
Platform FPGA Test Phases
• Parallel Test Approach to accelerate product qualification
• 3 SEE Consortium Tiger Teams: Fabric, Processor, Serial
Transceiver
Static
Dynamic
Mitigation
(1Q05)
(2Q05)
(3Q05)
FPGA Fabric
and Static Cells
V-2pro
PowerPC
Processor & IP
V-2pro
Multi-Gigabit
Serial Transceivers
Special Solutions
V-4
V-4
V-2pro
V-4
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Dose Rate Testing
• Current Test Program
• Historical Testing
– XC2VP40
– XC4036XL
• Work is funded by MDA
• Testing is being done by a consortium
• Testing was done by Lockheed
• Testing range of 1.0E7 to 4.0E11
(20 nsec pulse) tested
• No data upset >1.3E9 to >3.0E9
• No latch-up beyond 4.0E11
•
– XCVR300E
• Testing done by ITT (MRC)
• Testing range of 6.3E7 to 3.0E9
• No upset until > 4.0E8 (non-epi) to
>1.0E9 (epi)
• No latch-up beyond 3.0E9
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•
•
•
•
14
consisting of AFRL, Crane, Xilinx and
Raytheon
Initial tests were run July 2004 at
Navsea Crane using 60 MeV electron
beam source utilized commercial
Virtex-IIpro performance board and
commercial V-IIpro parts
Tests to compare RH (epi) performed
in November 2004 at Navsea Crane
No upset until > 3.0E8
RH (epi) no POR until >1.0E9
No Latch-up through >1.0E10
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TMRTool
• Software development tool to automatically implement
TMR customer designs optimized for Xilinx FPGAs
• Result of Xilinx/Sandia National Labs partnership
– Released to Production in Sept 2004
• Support all design entry methods and HLLs
– NGO & NGC based input
– EDIF based output
• OS Support
– Windows 2000/XP GUI Support
– Windows/UNIX PERL Command Line Support
• Supports ISE 5.2i, 6.1i, 6.2i
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TMRTool Netlist Flow
Xilinx Design Flow
Design Entry
(Verilog, VHDL, Schematics)
Design
Verification
Functional
Simulation
Synthesis
(XST, Synplify, …)
Implementation
Timing
Simulation
Translate
Map
Static Timing
Analysis
PAR
Download
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RadHard by Design Program
SEU Immune Reconfigurable FPGA (SIRF)
Configuration
Memory
Block Memory
Control Logic
Clocking & Clock
Mgmt
Logic Fabric
DSP Fabric
RocketIO™
Multi-Gigabit Transceiver
SelectIO
PowerPC™
Virtex-4
Silicon Floorplan
Phase-1: Design Feasibility, Test Chip
Phase-2: Chip Development
Phase-2A: Advanced Features
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SIRF Radiation Goals
Total Dose
Dose Rate
Latch up
Upset
SEE
Latch up
Upset
Functional
Interrupt
Bogrow
> 300 krad(Si) (requirement)
> 1 Mrad(Si) (goal)
> 11010 rad(Si)/sec
> 1109 rad(Si)/sec (requirement)
> 5109 rad(Si)/sec (goal)
none up to LET > 100 MeV-cm2/mg
threshold LET > 40 MeV-cm2/mg,
error rate < 110-10 errors/bit-day (requirement)
threshold LET > 100 MeV-cm2/mg,
error rate < 110-10 errors/bit-day (goal)
threshold LET > 40 MeV-cm2/mg,
error rate < 110-10 errors/bit-day (requirement)
threshold LET > 100 MeV-cm2/mg,
error rate < 110-10 errors/bit-day (goal)
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Advanced Packaging
• CG717
o 35 x 35mm body, 1.27mm pitch, cavity-up
o Footprint compatible with the BG728
o Developed for the 2V3000
o Wire Bond, gold
o Au-Sn lid (hermetically sealed)
• CF1144
o 35 x 35mm body, 1.00mm pitch
o Footprint compatible with the FF1152
o Developed for the 2V6000
o Flipchip with high lead balls, MSL1
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Enhanced Flow – In Development
Hermetic Wire Bond Ceramic Flip Chip
Mask set control
Traceability
Wafer Lot Acceptance
Non-destructive bond pull
Internal visual
Constant acceleration
PIND
Serialization
Pre burn-in electrical
Static burn in
Post burn-in electrical
Delta calculations
PDA
Dynamic burn-in
Post burn-in electrical
Delta calculations
PDA
Final electrical
X-ray
External Visual
Group A
Group B
Group C
Group D
Group E
Data summary
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X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
20
Flip
Flip
Flip
Flip
X
X
X
chip equivalent
X
chip equivalent
N/A
X
X
X
X
X
X
X
X
X
X
X
N/A
X
X
chip equivalent
X
chip equivalent
X
X
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Summary
• Virtex-4 architecture and design methodology enables
rapid development of Platform-specific FPGAs with
embedded cores
• Advances in 90nm chip design resulted in optimized
performance, lower power, and first-silicon success of
Virtex-4
• SEE Consortium primary vehicle for radiation
characterization testing (US and European)
• Rad Tolerant program will continue with concurrent
phase-in of Rad Hard by Design program
• Advanced packaging and enhanced process flows
integral part of overall development efforts
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