Programmable Logic Device
Devices and Applications
Topics
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Architecture and Characteristic of PLD
FPGA Devices
Development Boards
FPGA Design Flow
Application in Signal Processing
Architecture of MAX 7000 MacroCell
Architecture of MAX 7000
Architecture of CycloneIII LE
Architecture of CycloneIII LAB
Connection
between
LABs
Difference between CPLD & FPGA
CPLD
FPGA
architecture
configuration
Product term
inner EEPROM
Look up Table
outer EEPROM
resource
Rich in combination
Rich in Flip-Flops
density
Low
High
Used Filed
Logical control
Complex algorithms
Other resource
－
EAB，PLL
security
good
So so
Global PLD Providers
• www.altera.com
– Inventor of CPLD，Best FPGA
• www.xilinx.com
– Inventor of FPGA，Best FPGA
• www.latticesemi.com
– Inventor of ISP
• www.actel.com
– For G.I. and Astrionics
CPLDs based on LUT
65nm、90nm、130nm
Low Cost FPGAs
40nm、65nm、90nm、
130nm High
Performance FPGAs
Low Cost FPGAs
with High Speed
transceiver
General CPLDs
structured ASICs
Better Performance
Lower Cost
Virtex Series
High Performance FPGAs
Vitrex-5 for latest
Vitrex-5 TXT，120Gbps in a single chip！
Spartan Series
Low Cost FPGAs
Spartan-3E for latest
CoolRunner Series CPLDs
CoolRunner-II for latest
• Anti-fuse FPGAs（ Radiation protection ，
perfect in security ）
• Flash Based FPGAs （ Inner configuration ，
perfect in security ）
• CPLDs (EEPROM)
• FPGAs with ViaLink（Low power cost，
perfect in security
• Earliest access to 40-nm technology AND a
low-risk path to production
• Highest density, highest performance, AND
lowest power
Stratix IV E FPGAs
• Up to 680K high-performance logic
elements(LEs)
• DSP blocks—with a parallel architecture and up to
1,360 embedded 18x18 multipliers running at
550 MHz, Stratix IV FPGAs deliver up to 748 GMACS
of DSP performance, a level unmatched by competing
devices
• TriMatrix memory—three memory block sizes with up
to 22.4 Mbits of embedded memory running
at 600 MHz
• An FPGA fabric that is two speed grades , or 35 percent,
faster than that of the nearest competitor
Transceiver-based Stratix IV GX FPGAs
• Up to 48 high-speed transceivers supporting
data rates of up to 8.5 Gbps, including hard
intellectual property (IP) protocols and signal integrity
optimization blocks
• Up to four hard IP blocks for PCI Express (PCIe)
compliant with PCIe Base Specification 2.0, 1.1, or 1.0,
supporting x1, x2, x4, and x8 configurations. You’ll also
have support for end-port and root-port applications.
• LVDS support up to 1.6 Gbps
• Up to four 72-bit high-speed DDR3 interfaces
at 1,067 Mbps (533 MHz)
256-bit key
AES encryption with FIPS-197 certification
• to 120,000 logic elements (LEs) and 4 Mbits
embedded memory .
• 260-MHz multiplier performance with the highest
multiplier-to-logic ratio in the industry.
• Robust clock management and synthesis with
dynamically reconfigurable and flexible phase-locked
loops (PLLs).
• Improved signal integrity with adjustable I/O
slew rates.
• Support for high-speed external memory
interfaces including DDR,DDR2, SDR SDRAM, and
QDRII SRAM.
• Support for I/O standards including LVTTL, LVCMOS,
SSTL, HSTL, PCI Express, LVPECL, LVDS, miniLVDS, RSDS, PPDS.
Example—Software Defined Radio
Example—Software Defined Radio
New LUT & LE Based CPLD
DE2 Development and Education Board
DE1 Development and Education Board
DE2-70 Development and Education Board
Cyclone III FPGA Starter Kit
Cyclone® III Development Kit
Spartan-3E Starter Kit
• Xilinx XC3S500E FPGA
• Xilinx XCF04 Platform Flash for storing FPGA
configurations
• St Microelectronics M25P16 16Mbit Serial Flash
• Intel TE28F128 (or JS28F128) 128Mbit StrataFlash
• Linear Technologies Power Supplies
• Texas Instruments TPS75003 Triple-Supply Power
Management IC
• SMSC LAN83C185 Ethernet PHY
• Micron 256Mbit DDR SDRAM
Quartus II
设计流程
• FPGA提供了极强的灵活性，可
让设计者开发出满足多种标准
的产品。
• FPGA所固有的灵活性和性能也
可让设计者紧跟新标准的变化，
并能提供可行的方法来满足不
断变化的标准要求。
• 由于成本、系统功耗和面市时
间等原因，许多通讯、视频和
图像系统已无法简单地用现有
DSP处理器来实现，FPGA尤其
适合于乘法和累加(MAC)等重复
性的DSP任务，最典型的就是
FFT。
复数乘法器RTL示意图
蝶形运算单元示意图
蝶形运算单元RTL示意图
1024点16位字长FFT耗时
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TI 公司TMS320C62x: 66 μs (定点)
TI 公司TMS320C64x: 36 μs (定点)
ADI公司TigerSharc TS101: 39 μs (浮点)
Xilinx公司的FFT IP核在100M外频时钟下达到
40.96 us,246MHz外频时钟下，速度达到25.49 μs
(定点)
• Altera公司的FFT IP核在100M外频时钟下达到
20.7us,在333MHz外频时钟下仅需要6.3 μs (定点)
• r-4 DIF FFT算法在100 MHz Virtex Ⅱ上以
多级串行同步流水方式 完成1 024 点、16
位复数点的块浮点FFT 处理时间为10. 2 μs
• SR DIF FFT算法在100MHz Virtex II Pro 上
以6级级联流水方式完成1024点、16 位复
数点的块浮点FFT 处理仅需要2.56 μs
• 采用16块工作在550MHz 的Virtex-5
XC5VSX240T（片内1056个DSP48E Slices）
的全并行结构同时处理两路信号可在1个
时钟周期内完成1024点16位SR-FFT，单路
处理时间小于2ns，处理延时仅为十几μs 。
谢谢！
2009.1.3