Stavelet Status Report
08.11.2010
Peter W Phillips
John Matheson, Bruce Gallop
Ashley Greenall, Matt Warren
Stavelet Numerology
The Stavelet
Hybrid
0
1
2
3
4
5
6
7
BCC
62
61
60
59
58
57
56
55
MUX
7
6
5
4
3
2
1
0
DEMUX
14/15
12/13
10/11
8/9
6/7
4/5
2/3
0/1
Coupling
DC
AC
AC
DC
AC
DC
AC
DC
Module
0
1
2
4
s/n
1
9
3
4
2
Stavelet IV Data at 22C
Leakage Current (microA)
18
16
FZ2 sensors
14
12
10
M0 FZ2 (sn 1)
M1 FZ1 (sn 9)
8
M2 FZ2 (sn 3)
M3 FZ2 (sn 4)
6
4
2
FZ1 sensor
0
0
50
100
150
200
250
Detector Bias (V)
All consistent with HPK data
3
Operating Information
• Stavelet cooling
– Pipes specified for CO2 but
running with water for now
– Water at 12.5C gives typically
45C on hybrids
• Stavelet has many power
options
– So far using Serial Power with
“M” shunt and PPB protection
– Other options to be tested later
(Spi, DC-DC, ...)
• Low Voltage from one of
– TTi TSX3510P mixed mode PSU
– TTi QMT series linear PSU
– Jan Stastny’s Current Source
• High Voltage from either
– SCTHV (VME version)
– Keithley (one channel)
• One Wire controller
– Commercial DS8490R unit
• Readout with HSIO
– Stavelet is main testbed for
development activity
– Firmware by Matt Warren with
contributions from Alexander
Law and Bruce Gallop
– Software by Peter and Bruce
– AC coupled LVDS, MLVDS
signals
– BCC V2, 80 MHz dclk
4
Hybrid Voltages vs Current
I
3.5
3.6
3.7
3.8
3.9
4.0
4.5
5.0
A
H0
H1
H2
H3
H4
H5
H6
H7
2.29
2.3
2.3
2.31
2.31
2.35
2.36
2.36
2.39
2.4
2.4
2.42
2.43
2.44
2.45
2.46
V (V)
2.55
2.5
Hybrid 0
2.45
Hybrid 1
Hybrid 2
Hybrid 3
2.4
Hybrid 4
2.476 2.485 2.495 2.496
Hybrid 5
2.35
Hybrid 6
2.499 2.496 2.504 2.498 2.495 2.504 2.501 2.496
Hybrid 7
2.499 2.496 2.504 2.498 2.495 2.504 2.501 2.496
2.3
2.499 2.496 2.504 2.498 2.495 2.504 2.501 2.496
V
V
V
V
V
V
V
V
2.25
0
2
4
6
I (A)
The ABCN-25 “M” shunt and the hybrid’s control circuitry work as expected:
Constant hybrid voltage from 4.0A
5
Thermal images of The Stavelet in Operation
All hybrids on
22.7V
5.09A
Slow control disables
odd hybrids
12.7V
5.09A
Slow control disables
even hybrids
Each hybrid may be bypassed using the PPB 1-wire operated shunt
Voltage differences consistent with 2.5V per hybrid
2.7V overheads: bus tape, bond wires, PPB PCBs, external cabling
6
Duty Cycle of Recovered BCO
with original bias network
2V5
Hybrid 0
55.5%
100pF
100pF
BCC
Stavelet driven with 50% duty input clock, duty increases along the stavelet,
resulting in 55.5% duty at the far end (hybrid 0). The offset introduced by the 5k
resistor in the above bias scheme was identified as the cause, as it reduces the
sensitivity of the receiver.
7
Duty Cycle of Recovered BCO
with revised bias network
Hybrid 0
49.9%
2V5
33k
33k
BCC board for hybrid 0 modified to above 4 resistor scheme, with zero offset. Not easy! Results
excellent, 50% duty obtained even for very low input amplitudes.
In this session, Carl reported results with an updated (1M / 10k / 1M) three resistor scheme
which gives a reduced but non zero offset, may be used to deliver a 50% duty clock along a full
8
length stave bus tape. However for now we’ll leave the stavelet components unchanged!
Optimisation of Stavelet Performance:
Basic Considerations
None of these have yet been found to have a significant effect
upon the overall system noise:
• TTi TSX3510P mixed mode power supply
– Alternate linear supply gave higher ENC.
• SCTHV (VME) power supplies
– Tested each module in turn using commercial Keithley unit. No
difference was observed.
• Temperature
– Run with three modules bypassed, fourth module at lower
temperature. Raise coolant temperature to compensate. To first
order, both runs give exactly the same noise.
Will need to iterate as dominant noise sources are eliminated.
9
Optimisation of Stavelet Performance :
End Of Stave card 3V3 Supply
3V3 measured on EoS (DC-DC)
3V3 measured on EoS (linear)
By default, the chips on EoS are powered from 3V3 DC-DC converter on the Interface
Board. Switching to a linear supply, the RMS noise on 3V3 is reduced from ~10 mV to
~5mV. This brings an immediate reduction to the noise of the hybrids nearest EoS.
10
Optimisation of Stavelet Performance:
HSIO powered from cheap,
floating, switch mode power brick
ISP
+48V
VSP
Data
Observe 2V dips on HSIO 48V rail every ~1.5mS
Observe 1.4V spikes on SP+ every ~6mS, with around 300mV baseline noise
However one might expect both of these phenomena to affect the stavelet’s ENC
=> What happens if we power HSIO from a linear supply?
11
Optimisation of Stavelet Performance :
HSIO powered from expensive,
floating, linear power supply
ISP
VSP
+48V
Data
Observe reduced 1.5V dips on HSIO 48V rail every ~1.5mS, but with added ringing
Still observe 1.4V spikes on SP+ line but with increased ~500mV baseline noise
Stavelet noise increased to ~1000 ENC!!!
Likely source of spikes of 1.5microS periodicity 12V DC-DC converter on HSIO
Further work required to determine if these have an impact upon stavelet noise
12
Optimisation of Stavelet Performance:
Shield Options
• The stavelet bus tape has
five separate shield pads
– One under each sensor (4 in
total)
– One over the MLVDS control
bus
• Bond pads permit the
sensor shield pads to be
– Connected to each other and
to the MLVDS shield
– AC or DC connected to the
Hybrid 0V planes
• There are many possible
shield configurations!
13
Stavelet ENC @2fC, JS CS II@5A
D
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
EARLY RESULT (1108-3), shield pads connected, EoS DC-DC
DC-DC
14
Stavelet ENC @2fC, TSX3510P@5A
D
C
A
C
A
C
D
C
A
C
D
C
A
C
D
C
RECENT RESULT (1267-3) shield pads separated, EoS linear
LIN
DEAD CHIP 
15
Stavelet ENC @2fC, TSX3510P@5A
D
C
A
C
A
C
D
C
A
C
D
C
A
C
D
C
RECENT RESULT (1284-6) shield pads separated, EoS linear
LIN
DEAD CHIP 
16
Stavelet ENC @1fC, TSX3510P@5A
D
C
A
C
A
C
D
C
A
C
D
C
A
C
D
C
RECENT RESULT (1284-3), shield pads separated, EoS linear
LIN
DEAD CHIP 
17
Stavelet NO, JS CS II@5A
D
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
EARLY RESULT (1108-6), shield pads connected, EoS DC-DC
18
Stavelet NO, JS CS II@5A
D
C
A
C
A
C
D
C
A
C
D
C
A
C
D
C
RECENT RESULT (1267-6) shield pads connected, EoS linear
LIN
19
Average Noise per column of ABCN-25 chips
ENC
800
700
600
500
Liverpool Single Module Data
Early Stavelet Result, 2fC
400
Recent Stavelet Result, 2fC
300
Recent Stavelet Result, 1fC
200
Stavelet, one at a time, 2fC
100
0
H0
C0
dENC
H0
C1
H1
C0
H1
C1
H2
C0
H2
C1
H3
C0
H3
C1
H4
C0
H4
C1
H5
C0
H5
C1
H6
C0
H6
C1
H7
C0
H7
C1
Extra noise with respect to Liverpool module data
120
Note: Liverpool data
for H0, H1, H6 & H7
more reliable than others
due to increased system
maturity at time of test...
100
80
Early Stavelet Result, 2fC
60
Recent Stavelet Result, 2fC
40
Recent Stavelet Result, 1fC
Stavelet, one at a time, 2fC
Mean:
45 ENC
38 ENC
31 ENC
33 ENC
20
0
-20
H0
C0
H0
C1
H1
C0
H1
C1
H2
C0
H2
C1
H3
C0
H3
C1
H4
C0
H4
C1
H5
C0
H5
C1
H6
C0
H6
C1
H7
C0
H7
C1
20
Summary
• The first stavelet has been successfully built
– Sensors not damaged during assembly
– Power Protection Boards may bypass hybrids
• Does not introduce extra noise
– Good analogue results recorded straight away
• First result: column mean 670 ENC
• Progress made to optimise the performance of the system
– Study of clock propagation along the tape
– Identification and Elimination of one external noise source
– Study of varied shield configurations
• Latest result: column mean 650 ENC with reduced spread
21
Outlook
• A few more shield configurations to try
– One being bonded today
• Continue to identify and eliminate possible external noise
sources
– Influence of HSIO DC-DC converters?
• Work in progress to define a full list of tests to be made
–
–
–
–
Double Trigger Noise tests
Operation at reduced temperature
Other power options
...
22