A MINI STEREO
DIGITAL AUDIO
PROCESSOR
(BEHAVIORAL MODEL)
Rohini
Ravichandran
Kaushik
Narayanan
ALGORITHM APPROACH
 Though a lot of audio processing algorithms are in practice,
the MSDAP uses the one which concentrates on FIR Digital
filtering, which implements the following function:
where,
X(n) – input audio sequence
Y(n) – output audio sequence
H(k) – filter coef ficients
N
- filter order (N=256)
ALGORITHM APPROACH (CONTD.)
 In order to reduce the hardware complexity, we use the
method of doing linear convolution by doing 1 -bit shift at a
time and transforming the function into a series of addition
and subtraction as shown below :
 Eqn.1
 Eqn.2
FRAMEWORK OF THE MSDAP – HOST
INTERFACE
 To reduce the extensive use of pins, the coefficients are also
sent from the controller to the MSDAP through the same input
data port (InputL / InputR) serially.
 If the controller issues a signal 𝑹𝒆𝒔𝒆𝒕_𝒏 = 𝟎, and the chip goes
into clearing mode, where all the register memories containing
input and coefficient samples are cleared, except for r j . Initially
InReady is latched to 0, but later after the reset completes, it is
asserted high and waits for any incoming input data
 If the signal InReady issued by the MSDAP is driven low, then the
controller will not transmit Dclk, Frame or any input samples to
the chip.
 If the signal InReady issued by the MSDAP is driven high, the
controller will transmit the Dclk to the clock port and the input
samples to InputL/InputR port. The Frame signal is asserted
every 16 clock cycles marking the end of every input sample.
SIGNAL FORMATS AND PROTOCOLS
 InputL/InputR
This is the input data stream through which the input samples
and the coef ficients are transmitted serially to the MSDAP.
All the input samples are 16 bit numbers in their two’s
complement form, the MSB bit being the sign bit in our case.
The input is read from this input data stream on every falling
edge of the Dclk. The reason behind this is to avoid loss of data
by giving it enough time to arrive at the MSDAP end
SIGNAL FORMATS AND PROTOCOLS
(CONTD.)
As the maximum filter order N = 256, the number of bits in r j is
8 bits. As the value is represented by 8 bits, the unused value
other than 8 LSB bits is set to 0.
For every Dclk, u j is loaded according to the given format, where
the unused bits are set to 0:
SIGNAL FORMATS AND PROTOCOLS
(CONTD.)
 Frame Signal
This is the signal that synchronizes the input and the output
samples. The frame is set high for one Dclk cycle when the MSB
of the input samples arrive and is then set low throughout the
input data frame. As the frame rate is chosen as 48 KHz, the
Dclk frequency is taken as 768 KHz (48 KHz x 16).
The input stream timing diagram is as follows:
SIGNAL FORMATS AND PROTOCOLS
(CONTD.)
There are total number of 16 r j values and 512 coefficients which
are sent to the MSDAP. For every input, MSB (sign -bit) is
transmitted first and then the LSB. Each frame is of 16bit size and
its start is denoted by a frame signal. Whenever the MSDAP is
ready to receive any input data, it asserts the InReady signal as
high. The input sample being 16 -bits, occupies the entire frame
length, unlike r j and coefficients where the unused MSB bits are
padded by the controller with the zeroes in order to occupy the
entire frame. The whole input data line transfer is done
synchronously with the Dclk.
 OutputL/OutputR
OutReady is set high, when the MSDAP transmits output samples
and is aligned to the Frame signal. The output data stream carries
the output samples serially from the MSDAP to the Controller. The
first but transmitted is the MSB (sign -bit) and the last one is LSB.
The output stream timing diagram is as follows:
SIGNAL FORMATS AND PROTOCOLS
(CONTD.)
The output frame is of 40 bits as mentioned in the previously
discussed sections. Whenever the output is being transmitted
by the MSDAP, the OutReady signal is set high for the total
duration of the output frame.
MIDTERM APPROACH
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Reading the data from the file
Transmitting the data to the MSDAP module
Issuing the required signals at the appropriate time
Computation of the data
Sending back the data to the testbench module
Checking for the Reset and Wait states
READING INPUT DATA
 The first step is to read the inputs from the data.in file.
 The entire data is read from the file and stored in an array
‘data’ of 15056 elements of size 16 bits.
[15:0]data[0]
Data.in
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
[15:0]data[15055]
FINITE STATE MACHINE
STATE 0
 In order to begin the entire procedure, a ‘start’ signal is
issued by the testbench to the MSDAP module.
 This signal marks the STATE 0.
 In this state, the chip begins the initialization process and
clears all the memory contents. After this is completed, the
chip enters into state 1 .
FINITE STATE MACHINE
STATE 1
 This is basically a waiting state, where we wait for the Rj
coef ficients. The InReady signal is set high,and when the
Frame is detected high, chip enters State 2.
FINITE STATE MACHINE
STATE 2
 In this state, the Rj coef ficients are read, and InReady is kept
high. Once all the Rj values are read, chip enters next state
(State 3)
FINITE STATE MACHINE
STATE 3
 Here we wait for the Coef ficient values to be received.
InReady still remains high, when Frame is asserted again, it
moves into State 4.
FINITE STATE MACHINE
STATE 4
 This is the reading state of the Coef ficient values. InReady is
kept high, in order to wait for the Coef ficient values. Once all
the values are loaded, chip enters State 5.
FINITE STATE MACHINE
STATE 5
 This is wait state for the Data values, where InReady is again
kept high. If Frame is detected to be high, there is a state
transition to State 6, the computation State. But if Reset_n
goes low, it transitions to State 7, the Reset State.
FINITE STATE MACHINE
STATE 6
 This is working state, of the MSDAP, where the inputs
samples, that are continuously read, are convoluted and
transmits the corresponding outputs. Again, if incase the
Reset_n signal is detected low, chip moves to State 7.
Whereas, if there are 800 consecutive zero input samples,
chip moves to the sleep state, the State 8.
FINITE STATE MACHINE
STATE 7
 In this state, InReady is set low, and all the input (except Rj
and Coef ficient data) and output samples are cleared. If
Reset_n is still low, chip remains in this state, else, it goes
back to wait state, State 5.
FINITE STATE MACHINE
STATE 8
 This state is the sleep mode of the MSDAP. In this state,
InReady is high, waiting for any non -zero sample on any of the
channels. On occurrence of such sample, chip goes back to
state 6. However, if Reset_n is detected low, chip goes to
state 7.
CONCLUSION

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Understood the application of the Processor
Specification for the chip is built
System setting is specified
Finite State Machine for the Chip is designed in verilog
Implemented the operation mode of MSDAP in Verilog