Computer Buses
For many of you who have depopulated
his/her breadboards, THANKS!
There are still some to be depopulated.
Please don’t forget to do it this week,
please.
Final Exam – Thur, Dec 11, 4:15-6:20
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Logic, Flip Flops, Timing, Synchronous / Asynchronous Circuits, Memory
Organization, Finite State Machines (FSM)
RISC / CISC Computers, MIPS Organization, MIPS Instructions, MIPS
Addressing, MIPS Frames / Context Switching, MIPS
Assembly/Machine Programming (will have MIPS card)
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Hamming Code
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Developing MIPS Datapaths, MIPS FSM Implementations, and
Alternative Microprogramming
Midterm ----------------------------------
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Pipelining - implementing, forwarding, handling branches
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Cache – Direct, Associative, Set Associative
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Virtual memory – Organization, Page Faults, and Look Aside Buffer
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IA-64 - Bundled Instructions /explicit parallel, predicated execution,
control speculation, speculative data loading, software pipelining /
unraveling loops (don’t expect you to know details of the IA-64)
I/O Devices & Buses – Magnetic Disks, Solid State Disks, Flash
Memory, Optical Disks, Magnetic Tape
- Organization, Implementation, Interrupts, Bus Control, DMA
60% on material covered after the midterm
Basic I/O System Example
Processor
Cache
Memory - I/O Bus
Main
Memory
I/O
Controller
I/O
Controller
Disk … Disk
Disk … Disk
Computer Buses
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The bus is a critical component of the Computer:
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They are shared components that provide the paths for all
parts of the computer to communicate with each other
They can reduce the complexity of communications between
computer components
They contain conduits for data, “addressing”, and
timing/control
They need a protocol that all users use
They can provide an easy way to evolve a computer system –
add components
They can be a serious bottleneck if not designed and used
appropriately
As systems grow, they need to evolve hierarchically
They can be parallel or serial
They can have data widths larger than the computer word
length
Types of Buses
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Processor-memory bus (maybe proprietary)
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Matched to the memory system to maximize the memoryprocessor bandwidth
Optimized for cache block transfers
Backplane bus (maybe industry standard)
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Short and high speed
The backplane is an interconnection structure within the chassis
Used as an intermediary bus connecting I/O busses to the
processor-memory bus
I/O bus (industry standard, e.g., SCSI, PCI,USB, Firewire)
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Usually is lengthy and slower
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Needs to accommodate a wide range of I/O devices
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Connects to the processor-memory bus or backplane bus
Bus Characteristics
Control lines: Master initiates requests
Bus
Master
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Bus
Slave
Data & Address lines
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Data lines: Data can go either way
Data, addresses, and complex commands
Control lines
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Signal requests and acknowledgments
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Indicate what type of information is on the data lines
Bus transaction consists of
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Master issuing the command (and address)
– request
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Slave receiving (or sending) the data
– action
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Defined by what the transaction does to memory
- Input – inputs data from the I/O device to the memory
- Output – outputs data from the memory to the I/O device
Buses
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What are the Bus design considerations?
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Accessibility
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Speed
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Reliability
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Extensibility
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Bottle necks
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Noise (electrical)
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Flexibility
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Ease of Interfacing
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Power
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Sharability
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Communication Protocol
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Length
Should Buses distribute Power?
Computer Bus
Buses are composed of three sets of lines
Not all devices will use all lines in each category
What does this improve?
What is gained here?
Where are the challenges here?
How about this one?
Selector and Multiplexor Channels
Parallel and Serial I/O
Daisy Chained “Bus”
USB Topology
Computer Bus
Control lines include:
Clock(s)
Interrupt Support
Bus Control
R/W
etc.
Bus Communications
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Bus Protocols
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Asynchronous
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Synchronous
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Memory Read / Writes ?
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I/O Read Writes?
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Peer communication – e.g. CPU to CPU
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Are communications verified?
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Is there error checking ?
Synchronous and Asynchronous Buses
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Synchronous bus (e.g., processor-memory buses)
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Includes a clock in the control lines and has a fixed protocol
for communication that is relative to the clock
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Advantage: involves very little logic and can run very fast
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Disadvantages:
- Every device communicating on the bus must use same clock rate
- To avoid clock skew, they cannot be long if they are fast
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Asynchronous bus (e.g., I/O buses)
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It is not clocked, so requires a handshaking protocol and
additional control lines (ReadReq, Ack, DataRdy)
Advantages:
- Can accommodate a wide range of devices and device speeds
- Can be lengthened without worrying about clock skew or
synchronization problems
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Disadvantage: slow(er)
Synchronous Bus
Asynchronous Bus Handshaking Protocol
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Output (read) data from memory to an I/O device
ReadReq
Data
Ack
1
2
addr
data
3
4
6
5
7
DataRdy
I/O device signals a request by raising ReadReq and putting the addr on
the data lines
1.
2.
3.
4.
5.
6.
7.
Memory sees ReadReq, reads addr from data lines, and raises Ack
I/O device sees Ack and releases the ReadReq and data lines
Memory sees ReadReq go low and drops Ack
When memory has data ready, it places it on data lines and raises
DataRdy
I/O device sees DataRdy, reads the data from data lines, and raises
Ack
Memory sees Ack, releases the data lines, and drops DataRdy
I/O device sees DataRdy go low and drops Ack
Asynchronous Bus
Physical Considerations
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How are the various components connected?
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Unidirectional / bidirectional
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And /Or combinational circuits
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Wired Or circuits
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Tri-state
Or configuration:
Normal Gate Output Stage:
Observe that the output is
always driven High or low.
What happens if we connect
two of these to the bus?
Wired OR
+5V
Now any new device can just be connected to the
bus anywhere.
If no device is pulling the bus line low, it is high A
NOR function
Tri-State
Now each device can either drive the line high,
drive it low, or
leave it open
Symbols
Buffer
Open Collector
Tri-State
Signal Considerations
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What about signal integrity?
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What about noise?
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Fanout
Drivers
What about length limitations?
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Bus termination
Characteristic Impedance
Terminated at Char Impedance
Not Terminated at Char Impedance
Termination comparisons
Open Termination
Short Termination
Proper Termination
A Typical I/O System
Processor
Interrupts
Cache
Memory - I/O Bus
Main
Memory
I/O
Controller
Disk
Disk
I/O
Controller
I/O
Controller
Graphics
Network
Interrupt Systems
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Interrupt Systems Allow Devices to request I/O Service
when THEY are ready
Process?
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Device given “permission” to generate an Interrupt Request
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Request an Interrupt of the present process (IF priority allows)
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On Request Acknowledge, provide “Vector” of Service Routine
(just like a memory read)
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CPU makes a context switch and begins the Service Routine
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On completion of the service, a context switchback occurs
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The original process continues where it left off
Bus Master
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A bus Master controls the bus
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Reads
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Writes
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Interrupt Request / Acknowledge
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Bus Master Request / Acknowledge
Why would there be multiple potential Bus Masters?
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Multiple Processor Shared Systems
One Processor can use the bus while another is doing internal
processing
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To accommodate the replacement of a “bad” bus master
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Sometimes there is a voting system to determine Bus Control
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Allows I/O devices to talk to memory or another I/O Device
without using the processor time
Bus Master
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How does a Bus Master System work?
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A potential Bus Master can Request the Bus Control
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On Acknowledgement / Grant the new Master Takes Control
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When there is a timeout due to no bus activity
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A Potential Bus Controller announces intention to take
control
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Unless there is an objection, it then takes Control
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If there are multiple requests
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There is an arbitration process to determine who takes
control
DMA (Direct memory Access)
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Is there some way to use the bus when the master is
not using it?
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Yes, its called a DMA
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To use the Bus, a device must request to DMA
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On Grant, the device can make multiple transfers and then
give up the Bus. During this time the Bus Master doesn’t use
the Bus (possibly goes to sleep)
How is it used?
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Typically, a device, like a Disk, requests the right to DMA
one word or a Block of Words to a memory “page”.
When granted, the Disk fills the Block – in a burst (while the
Bus Master perhaps sleeps) or one word at a time when the
bus is not busy.
When the Block has been transferred, the Device may likely
Interrupt the CPU to report the transaction is completed.
Some DMA Configurations
The Need for Bus Arbitration
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Multiple devices may need to use the bus at the same
time so must have a way to arbitrate multiple requests
Bus arbitration schemes usually try to balance:
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Bus priority – the highest priority device should be serviced first
Fairness – even the lowest priority device should never be
completely locked out from the bus
Bus arbitration schemes can be divided into four
classes
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Daisy chain arbitration – see next slide
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Centralized, parallel arbitration – see next-next slide
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Distributed arbitration by self-selection – each device wanting the
bus places a code indicating its identity on the bus
Distributed arbitration by collision detection – device uses the bus
when its not busy and if a collision happens (because some other
device also decides to use the bus) then the device tries again later
(Ethernet)
Daisy Chain Bus Arbitration
Device 1
Highest
Priority
Ack
Bus
Arbiter
Device N
Lowest
Priority
Device 2
Ack
Ack
Release
Request
wired-OR
Data/Addr
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Advantage: simple
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Disadvantages:
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Cannot assure fairness – a low-priority device may be locked
out indefinitely
Slower – the daisy chain grant signal limits the bus speed
Centralized Parallel Arbitration
Device 1
Ack1
Bus
Arbiter
Device 2
Request1
Device N
Request2
RequestN
Ack2
AckN
Data/Addr
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Advantages: flexible, can assure fairness
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Disadvantages: more complicated arbiter hardware
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Used in essentially all processor-memory buses and
in high-speed I/O buses
Layering – Example: OSI Network Layers
International Standards Organization’s (ISO) Open Systems Interconnection (ISO) Model:
•The Physical Layer describes the physical properties of the various communications
media, as well as the electrical properties and interpretation of the exchanged signals.
Example: this layer defines the size of Ethernet coaxial cable, the type of BNC connector used, and the
termination method.
•The Data Link Layer describes the logical organization of data bits transmitted on a
particular medium.
Example: this layer defines the framing, addressing and check-summing of Ethernet packets.
•The Network Layer describes how a series of exchanges over various data links can
deliver data between any two nodes in a network.
Example: this layer defines the addressing and routing structure of the Internet.
•The Transport Layer describes the quality and nature of the data delivery.
Example: this layer defines if and how retransmissions will be used to ensure data delivery.
•The Session Layer describes the organization of data sequences larger than the
packets handled by lower layers.
Example: this layer describes how request and reply packets are paired in a remote procedure call.
•The Presentation Layer describes the syntax of data being transferred.
Example: this layer describes how floating point numbers can be exchanged between hosts with
different math formats.
•The Application Layer describes how real work actually gets done.
Example: this layer would implement file system operations.
Simple Example OF 7 Layer OSI Model
Application Layer: Set of C Instructions, Set of Data
{I0 I1 I2 …. IN Do D1 D2 … Dm}
Presentation Layer: ASCII Coding
{ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}
Session Layer: What process at computer x is communicating with what process at computer y
{X4 Y6 {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}}
Transport Layer: Guaranteed Transmission, sequentially numbered packets of 4096 bytes
{GT4 P34 {X4 Y6 {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}} PCKSUM}
Network Layer: Path through Network
{N23 N3 N53 {GT4 P34 {X4 Y6 {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}} PCKSUM}}
Data Link Layer: Serial 256 bytes per frame
{STRT T{N23 N3 N53 {GT4 P34 {X4 Y6 {ASC {I0 I1 I2 …. IN Do D1 D2 … Dm}}}
PCKSUM}}CHKSM}
Physical Layer: 9600Baud, Coax cable - {Start {….}Parity Stop Stop}
Ethernet packet
Bob Metcalf’s Ethernet Concept - 1976