Self-Biased, High-Bandwidth, LowJitter 1-to-4096 Multiplier Clock
Generator PLL
Based on a presentation by:
John G. Maneatis1, Jaeha Kim1, Iain McClatchie1,
Jay Maxey2, Manjusha Shankaradas2
True Circuits, Los Altos, CA1
Texas Instruments, Dallas, TX2
PDF file of JSSC paper linked at class web page.
Clock Generator PLLs for ASICs
FREF
Network
Processor
Graphics
Processor
I/O
Controller
Your
ASIC
PLL
FOUT
N
 Most ASICs PLLs for clock generation, but …
 Use different frequencies and multiplication
2
Optimal PLL Design
 For each FOUT and N, one must adjust loop
parameters for both minimum jitter and stability
 For clock generators (track input clocks)
(wREF = 2p·FOUT/N)
 Loop bandwidth : wN ~ wREF/20
 Damping ratio : z ~ 1
 Third-order pole : wC ~ wREF/2
 Circuit parameters (e.g. ICH, R) must vary with
FOUT and N!
3
Addressing Diverse Specifications
 Designing a different PLL for each ASIC
 Easier to meet the specification, but …
 Verifying all designs is difficult and costly
 Our Goal: One PLL design for all ASICs
 Only one design needs verification, but …
 Loop parameters must adjust automatically
to satisfy wide range of FOUT and N
4
Challenges
 Self-biased PLLs [Maneatis ‘96] adjust for FOUT
 Achieve fixed wN/wREF and z indep. of PVT
 But, Self-Biased PLLs do NOT adjust for N
 wN/wREF and z vary with N (want fixed)
 wC/wREF varies with N (want fixed)
 This talk extends Self-Biased PLLs for wide
ranges of N with a new loop filter network
5
Outline







Introduction
Review of Self-Biased PLLs
Pattern Jitter Issues
Loop Filter Architecture
Implementation of Key Circuits
Measured Results
Conclusions
6
Second-Order PLLs
C1
CKREF
CKFB
UP
PFD
DN
R
CP
ICH
VCTL
VCO
KV
CKOUT
N
PO (s)
1  2  z  (s / wN )
 N
PI(s)
1  2  z  (s / wN )  (s / wN )2
wN 
1 I K  1
N CH V C1
z  1  wN  R  C1
2
7
Second-Order PLLs
C1
CKREF
CKFB
UP
PFD
DN
R
CP
ICH
VCTL
VCO
KV
CKOUT
N
VCTL
1
 I CH (
 R)
CS
Oscillation frequency is supposed to be controlled by VCTL,
that is by ICH/CS + ICH*R.
In Ring Oscillators, frequency is more easily controlled by
current, through tail biasing voltage.  want tail current to
have two components: ICH/CS + ICH*R.
8
Self-Biased PLLs
CKREF
CKFB
UP
PFD
DN
CP
xID
1/gm
VFF
ID
VBN
C1
CP
xID
VCTL
VCO
KV
=k/CB
CKOUT
Replica-Feedback
Biasing
N
R  1/ gm
ICH  x  ID
FVCO  gm CB
VBN biases the tail current in Ring Oscillator buffer stages.
1
So want ID to have components: I CH (
 R)
CS
9
Self-Biased PLLs
CKREF
CKFB
UP
PFD
DN
CP
xID
VFF
1/gm
ID
VBN
C1
CP
xID
VCTL
VCO
KV
=k/CB
CKOUT
Replica-Feedback
Biasing
N
Op Amp adjust VBN so that NMOST ID matches currents in
1/gm and that from top charge pump.
Notice: VCTL = VDD – ICH / sC1 d
ID = (VDD – VCTL)gm + ICH-ff = ICH (1/sC1 + 1)
Hence VBN will generate I-tail proportional to ICH (1/sC1 + 1)
10
Maneatis self bias generator
From 1996 Maneatis paper, which is very widely reference.
PDF file linked at web page.
11
Self-Biased PLLs
 With Self-Biased PLLs
wN wREF  1  x  N  CB C1 ~ x  N
2p
z  1  x N  C1 CB ~ x N
4
 wN/wREF and z are constant with FOUT,
BUT not with N
12
Pattern Jitter / Spurious Noise
 Phase corrections every rising reference edge
can cause disruptions to nearby output cycles
 Periodic noise pattern repeats every ref. cycle
or N output cycles
CKREF
VCTL
CKOUT
SHORT
 Typical causes
 Charge pump imbalances or leakage
 Jitter in reference clock (aperiodic result)
13
Shunt Capacitor
 Use third-order pole to extend disturbance with
reduced amplitude over many output cycles
CKREF
VCTL
FILTERED
CKOUT
 Problem with varying N using fixed capacitor
 Extended number of cycles NOT function of N
 Too few for large N
 Pattern jitter
 Too many for small N  Instability
14
Proposed Loop Filter
 Use switched capacitor filter network to
 Output scaled amplitude error signal with N
output cycle duration [Maxim ’01]
CKREF
VCTL
FILTERED
CKOUT
 Want a simple solution using this approach that
is compatible with Self-Biased PLLs
15
Original Filter Network
UP
DN
CP
VFF
1/gm
VBN
C1
CP
Replica-Feedback
Biasing
VCTL
 Only need to filter feed-forward path
16
Sampled Feed-Forward Network
UP
DN
CP
VRST
CP
C2
VFF
gm
C1
1/gm
VBN
Replica-Feedback
Biasing
VCTL
 Sample phase error and generate proportional
current that is held constant for N·TOUT
 Sampled error is reset at end of ref. cycle
 Need VRST = VCTL as zero bias level
17
Complete Filter Network
UP
DN
CP
C2
VFF
1/gm
gm
C1
VBN
Replica-Feedback
Biasing
VCTL
 Reset C2 to VCTL directly
 Eliminates C1 charge pump
 Equivalent feed-forward control gain
QO ~ N · QI
18
Loop Dynamics
 With this new loop filter network we achieve
wN wREF ~ x  N
z ~ QO QI   x N ~ x  N
 Need to keep wN/wREF and z constant with N
 Just scale charge pump current with 1/N (=x)
 More detailed analysis will show
wN wREF  1  CB C1
2p
z  1  CB  C1 C2
4
 Both are independent of FOUT, N, and PVT!
19
Complete Self-Biased CGPLL
Loop Filter
UP
DN
gm(VFS1+VFS2)
C2
CP1
VFS1
VFF
CKREF
CKFB
PFD
VBC
C1
1/gm
VBP
VBN
VCO
CKOUT
C2 VCTL
CP2
VBC
VFS2
Replica-Feedback
VCO Bias Gen.
Charge Pump Bias Gen.
(Prog. 1/N Current Mirror)
Divide Ratio
(N=1...4096)
Clock
Divider
20
Self-Biased Filter Network
CP1
C2
VFS1
en
VFF
S1
VBN
UP
DN
CP2
en
VFS2
C2
S2
VBN
Select
Control
C1
VCTL
21
Filter Network Reset Switches
VDD+VCTL
VBR  VCTL
VCTL
sel_boosted
VBN
VFS
VCTL
SEL_B
SEL
 Can switch to VCTL independent of voltage level
22
Filter Network Reset Switches
VDD+VCTL
VBR  VCTL
VCTL
sel_boosted
VFS
VCTL
C
D
A
B
SEL_B
VBN
SEL
When un-selected, sel = 0, sel_B = 1 (VDD). V_B = VDD,
V_D = VDD + V_CTL, V_A = 0, V_C = V_BR = V_CTL.
V_CA charged to V_CTL
23
Filter Network Reset Switches
VDD+VCTL
VBR  VCTL
VCTL
sel_boosted
VFS
VCTL
C
D
A
B
SEL_B
VBN
SEL
When selected, sel_B = 0, sel = 1 (VDD). V_A = VDD, V_C
= VDD + V_CTL, V_B = 0, V_D = V_BR.
V_DB charged to V_BR or V_CTL
24
Inverse-Linear Current Mirror
 Need to generate ICH = ID / N
 Use switches to adjust device size on input side
 For N=1~4096, need 12 binary weighted legs
 Need size range of 2048:1  Too much area!
IIN
IOUT
VBD
S5
x32
S4
x16
S3
S2
x8
S1
x4
S0
x2
x1
25
Multi-Stage Linear CM
 Solution to size problem with LINEAR control
 Use multiple device groups operating at
different but ratioed current densities
 Can have large ranges using small devices
IIN
IOUT
8:1
VBD
S 5 S4 S3
x4 x2 x1
S 2 S1 S0
x4 x2 x1
26
Multi-Stage Inverse-Linear CM
 Just diode connect multi-stage linear current
source and use as input side of current mirror
 Can output gate bias of any device group
 Stable as long as gain blocks reduce currents
IIN
VBD
IOUT
8:1
S 5 S4 S 3
x4 x2 x1
S 2 S1 S 0
x4 x2 x1
27
Complete Current Mirror
IOUT
IIN
IIN
VBN

1
N
IOUT
VBC
(N = 1 … 4096)
VBD
S11 S10 S9
E3
S8 S7 S 6
E3
8:1
E2
S5 S4 S3
E2
8:1
S2 S1 S0
x4 x2 x1
x1
8:1
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Voltage-Controlled Oscillator
VCO Replica-Feedback Bias Generator
Buffer Stage
VBP
VFF
VBP
VOVI +
VREP
VBN
VCTL
VTAIL
VO +
VI -
VBN
11-Stage Ring Oscillator
VBP
CK+
CK+
CK-
CK-
VBN
29
Buffer Tail Node Matching
VREP
V
V
VTAIL
time
ID I I
L
H
V
V
Higher VDD
VDS
30
Modified VCO
VCO Replica-Feedback Bias Generator
Buffer Stage
VBP
VFF
VBP
VOVI +
VBN
VCTL
VO +
VI VBN
VTAIL
(SHARED)
11-Stage Ring Oscillator
VBP
CK+
CK+
CK-
CKVTAIL
VBN
31
Static Supply Sensitivity
32
PLL Implementation
0.13mm N-well CMOS
Nominal Supply Voltage
1.5V (designed for 1.2V)
Total Occupied Area
0.38 x 0.48mm2
VCO Frequency Range
30 ~ 650 MHz
Multiplication Factor Range
N = 1 ~ 4096
Power Dissipation
7mW @ 240 MHz, 1.5V
PLL
Process Technology
Loop Filter
Capacitors
33
Measured Jitter vs N (240MHz)
34
PLL Jitter Measurement Summary
35
Conclusions
 Proposed PLL achieves wide N and FOUT range
 PLL is self-biased with constant loop dynamics
(wN/wREF, z ), independent of N, FOUT , and PVT
 Sampled feed-forward network suppresses
pattern jitter with effective wC that tracks wREF
 Achieves relatively constant period jitter of less
than 1.7% as N is scaled from 1 to 4096
36
References
 J. Maneatis et al., “Self-biased high-bandwidth low-jitter 1-to-4096
multiplier clock generator PLL,” in IEEE Int. Solid-State Circuits Conf.
Dig. Tech. Papers, Feb. 2003, pp. 424–425.
 J. Maneatis, “Low-jitter process-independent DLL and PLL based on
self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723–
1732, Nov. 1996.
 A. Maxim et al., “A low-jitter 125–1250 MHz process-independent 0.18
m CMOS PLL based on a sample-reset loop filter,” in IEEE Int. SolidState Circuits Conf. Dig. Tech. Papers, Feb. 2001, pp. 394–395.
 T. C. Lee and B. Razavi, “A stabilization technique for phase-locked
frequency synthesizers,” in Symp. VLSI Circuits Dig. Tech. Papers,
June 2001, pp. 39–42.
 J. Maneatis and M. Horowitz, “Precise delay generation using coupled
oscillators,” IEEE J. Solid-State Circuits, vol. 28, pp. 1273–1282, Dec.
1993.
37