24.2: Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock Generator PLL John G. Maneatis1, Jaeha Kim1, Iain McClatchie1, Jay Maxey2, Manjusha Shankaradas2 True Circuits, Los Altos, CA1 Texas Instruments, Dallas, TX2 J. G. Maneatis, Presented at ISSCC 2003 Clock Generator PLLs for ASICs Network Processor Graphics Processor I/O Controller Your ASIC FREF PLL FOUT ÷N Most ASICs PLLs for clock generation, but … Use different frequencies and multiplication 2 J. G. Maneatis, Presented at ISSCC 2003 Optimal PLL Design For each FOUT and N, one must adjust loop parameters for both minimum jitter and stability For clock generators (track input clocks) (ωREF = 2π·FOUT/N) Loop bandwidth : ωN ~ ωREF/20 Damping factor : ζ ~ 1 Third-order pole : ωC ~ ωREF/2 Circuit parameters (e.g. ICH, R) must vary with FOUT and N! 3 J. G. Maneatis, Presented at ISSCC 2003 Addressing Diverse Specifications Designing a different PLL for each ASIC Easier to meet the specification, but … Verifying all designs is difficult and costly Our Goal: One PLL design for all ASICs Only one design needs verification, but … Loop parameters must adjust automatically to satisfy wide range of FOUT and N 4 J. G. Maneatis, Presented at ISSCC 2003 Challenges Self-biased PLLs [Maneatis ‘96] adjust for FOUT Achieve fixed ωN/ωREF and ζ indep. of PVT But, Self-Biased PLLs do NOT adjust for N ωN/ωREF and ζ vary with N (want fixed) ωC/ωREF varies with N (want fixed) This talk extends Self-Biased PLLs for wide ranges of N with a new loop filter network 5 J. G. Maneatis, Presented at ISSCC 2003 Outline Introduction Review of Self-Biased PLLs Pattern Jitter Issues Loop Filter Architecture Implementation of Key Circuits Measured Results Conclusions 6 J. G. Maneatis, Presented at ISSCC 2003 Second-Order PLLs C1 CKREF CKFB UP PFD DN R CP ICH VCTL VCO KV CKOUT ÷N PO (s) 1 + 2 ⋅ ζ ⋅ (s / ωN ) = N⋅ PI(s) 1 + 2 ⋅ ζ ⋅ (s / ωN ) + (s / ωN )2 ωN = 1 ⋅I ⋅K ⋅ 1 N CH V C1 ζ = 1 ⋅ ωN ⋅ R ⋅ C1 2 7 J. G. Maneatis, Presented at ISSCC 2003 Self-Biased PLLs CKREF CKFB UP PFD DN CP x⋅ID 1/gm VFF ID VBN C1 CP x⋅ID VCTL VCO KV =k/CB CKOUT Replica-Feedback Biasing ÷N R = 1/ gm ICH = x ⋅ ID FVCO = gm CB 8 J. G. Maneatis, Presented at ISSCC 2003 Self-Biased PLLs With Self-Biased PLLs ωN ωREF = 1 ⋅ x ⋅ N ⋅ CB C1 ~ x ⋅ N 2π ζ = 1 ⋅ x N ⋅ C1 CB ~ x N 4 ωN/ωREF and ζ are constant with FOUT, BUT not with N 9 J. G. Maneatis, Presented at ISSCC 2003 Pattern Jitter / Spurious Noise Phase corrections every rising reference edge can cause disruptions to nearby output cycles Periodic noise pattern repeats every ref. cycle or N output cycles CKREF VCTL CKOUT SHORT Typical causes Charge pump imbalances or leakage Jitter in reference clock (aperiodic result) 10 J. G. Maneatis, Presented at ISSCC 2003 Shunt Capacitor Use third-order pole to extend disturbance with reduced amplitude over many output cycles CKREF VCTL FILTERED CKOUT Problem with varying N using fixed capacitor Extended number of cycles NOT function of N Too few for large N → Pattern jitter Too many for small N → Instability 11 J. G. Maneatis, Presented at ISSCC 2003 Proposed Loop Filter Use switched capacitor filter network to Output scaled amplitude error signal with N output cycle duration [Maxim ’01] CKREF VCTL FILTERED CKOUT Want a simple solution using this approach that is compatible with Self-Biased PLLs 12 J. G. Maneatis, Presented at ISSCC 2003 Original Filter Network UP DN CP VFF 1/gm VBN C1 CP Replica-Feedback Biasing VCTL Only need to filter feed-forward path 13 J. G. Maneatis, Presented at ISSCC 2003 Sampled Feed-Forward Network UP DN CP VRST CP C2 VFF gm C1 1/gm VBN Replica-Feedback Biasing VCTL Sample phase error and generate proportional current that is held constant for N·TOUT Sampled error is reset at end of ref. cycle Need VRST = VCTL as zero bias level 14 J. G. Maneatis, Presented at ISSCC 2003 Complete Filter Network UP DN CP C2 VFF 1/gm gm C1 VBN Replica-Feedback Biasing VCTL Reset C2 to VCTL directly Eliminates C1 charge pump Equivalent feed-forward control gain QO ~ N · QI 15 J. G. Maneatis, Presented at ISSCC 2003 Loop Dynamics With this new loop filter network we achieve ωN ωREF ~ x ⋅ N ζ ~ (QO QI ) ⋅ x N ~ x ⋅ N Need to keep ωN/ωREF and ζ constant with N Just scale charge pump current with 1/N (=x) More detailed analysis will show ωN ωREF = 1 ⋅ CB C1 2π ζ = 1 ⋅ CB ⋅ C1 C2 4 Both are independent of FOUT, N, and PVT! 16 J. G. Maneatis, Presented at ISSCC 2003 Complete Self-Biased CGPLL Loop Filter UP DN VFF CKREF CKFB CP1 gm(VFS1+VFS2) C2 VFS1 PFD VBC C1 1/gm VBP VBN VCO CKOUT C2 VCTL CP2 VBC VFS2 Replica-Feedback VCO Bias Gen. Charge Pump Bias Gen. (Prog. 1/N Current Mirror) Divide Ratio (N=1...4096) Clock Divider 17 J. G. Maneatis, Presented at ISSCC 2003 Self-Biased Filter Network CP1 en UP DN CP2 en Select Control C2 VFS1 VFF S1 VFS2 C2 VBN S2 C1 VBN VCTL 18 J. G. Maneatis, Presented at ISSCC 2003 Filter Network Reset Switches VDD+VCTL VBR ≈ VCTL VCTL sel_boosted VBN VFS VCTL SEL_B SEL Can switch to VCTL independent of voltage level 19 J. G. Maneatis, Presented at ISSCC 2003 Inverse-Linear Current Mirror Need to generate ICH = ID / N Use switches to adjust device size on input side For N=1~4096, need 12 binary weighted legs Need size range of 2048:1 → Too much area! IIN IOUT VBD S5 x32 S4 x16 S3 S2 x8 S1 x4 S0 x2 x1 20 J. G. Maneatis, Presented at ISSCC 2003 Multi-Stage Linear CM Solution to size problem with LINEAR control Use multiple device groups operating at different but ratioed current densities Can have large ranges using small devices IIN IOUT 8:1 VBD S 5 S4 S3 x4 x2 x1 S2 S1 S0 x4 x2 x1 21 J. G. Maneatis, Presented at ISSCC 2003 Multi-Stage Inverse-Linear CM Just diode connect multi-stage linear current source and use as input side of current mirror Can output gate bias of any device group Stable as long as gain blocks reduce currents IIN VBD IOUT 8:1 S 5 S4 S 3 x4 x2 x1 S 2 S1 S0 x4 x2 x1 22 J. G. Maneatis, Presented at ISSCC 2003 Complete Current Mirror IOUT IIN IIN VBN ∝ 1 N IOUT VBC (N = 1 … 4096) VBD S11 S10 S9 E3 S8 S7 S6 E3 8:1 E2 S5 S4 S3 E2 8:1 8:1 S2 S1 S0 x4 x2 x1 x1 23 J. G. Maneatis, Presented at ISSCC 2003 Voltage-Controlled Oscillator VCO Replica-Feedback Bias Generator Buffer Stage VBP VFF VBP VREP VCTL VBP VOV I+ VBN VTAIL VO + VI- VBN 11-Stage Ring Oscillator CK+ CK+ CK- CK- VBN 24 J. G. Maneatis, Presented at ISSCC 2003 Buffer Tail Node Matching VREP V ∆V VTAIL time ID ∆I ∆I L H ∆V ∆V Higher VDD VDS 25 J. G. Maneatis, Presented at ISSCC 2003 Modified VCO VCO Replica-Feedback Bias Generator Buffer Stage VBP VFF VBP VOV I+ VBN VCTL VBP VO + VIVBN VTAIL (SHARED) 11-Stage Ring Oscillator CK+ CK+ CK- CKVTAIL VBN 26 J. G. Maneatis, Presented at ISSCC 2003 Static Supply Sensitivity 27 J. G. Maneatis, Presented at ISSCC 2003 PLL Implementation 0.13µm N-well CMOS Nominal Supply Voltage 1.5V (designed for 1.2V) Total Occupied Area 0.38 x 0.48mm2 VCO Frequency Range 30 ~ 650 MHz Multiplication Factor Range N = 1 ~ 4096 Power Dissipation 7mW @ 240 MHz, 1.5V PLL Process Technology Loop Filter Capacitors 28 J. G. Maneatis, Presented at ISSCC 2003 Measured Jitter vs N (240MHz) 29 J. G. Maneatis, Presented at ISSCC 2003 Conclusions Proposed PLL achieves wide N and FOUT range PLL is self-biased with constant loop dynamics (ωN/ωREF, ζ ), independent of N, FOUT , and PVT Sampled feed-forward network suppresses pattern jitter with effective ωC that tracks ωREF Achieves relatively constant period jitter of less than 1.7% as N is scaled from 1 to 4096 30
