Phase Locked Loops
Introduction
Phase locked loops (PLLs) allow the creation of a precise frequency
from an imperfect frequency source. Furthermore, the generated frequency
can be varied over a range of values. PLLs are often employed in RF
applications as well as digital circuits as a clock. Although PLLs have
existed since the 1930's, they recently found much wider usage and grown
in sophistication. Several commercial applications of PLLs will be
explored, followed by a detailed description of their operation.
Commercial Applications
Clock Recovery
Some signals are transmitted without a clock signal, examples
include the data that is read off of a hard disk platter, or fiber optic
telecommunications. In these cases, the clock signal must be generated
from the data stream itself. The Analog Devices AD808 is a device, that
when combined with a preamplifier, can serve as a fiber optic OC-12
receiver. It has two control loops, the first of which locks onto the
frequency of the transmitted signal, then gives control to the other.
The second control loops then maintains phase lock with the input. The
AD808 is capable of bit rates up to 622Mbps and has a unit cost of $14.21
[1].
Clock Generation
Another Analog Devices chip, the AD9516, generates a clock signal
that can be used by digital electronics. It has a built in oscillator
with phase locked loop that can operate between 2.55 Ghz and 2.95 Ghz.
It provides 14 clock outputs, with each pair of outputs having its own
clock divider. Thus, a variety of output frequencies are available
simultaneously. It is available for $14.88 [2].
Cellular Communications
The AD6548 is an ic smaller than a penny that implements all of the
transmit and receive functions of a cell phone. It supports quad-band
GSM/GPRS communications with on board PLLs, LC oscillators, and variable
gain low noise amplifiers. It even includes a crystal reference. With
the addition of a DSP chip and a general purpose microprocessor, the
engineer has all of the major building blocks of a cell phone. Pricing
is not available from the manufacturer [3].
Underlying Technology
Design
A Phase locked loop consists of an inexpensive variable frequency
oscillator, which employs negative feedback to stabilize its output
frequency. The oscillator can be anything from a ring oscillator to a LC
circuit with variable capacitance. The output of the oscillator is fed
to a divider which converts the output to a lower frequency. The output
of the divider is then compared with a high-precision frequency
reference, usually a crystal oscillator. The device that performs this
comparison is called a phase detector. The phase detector produces a
current which is proportional to the phase difference between the
reference oscillator and the output of the divider. This current is then
used to control the variable oscillator[4]. In this way, the output of
the PLL can be any multiple of the reference frequency that the variable
oscillator is capable of producing.
Recent Advances
PLLs with an integer divider are known as integer-N PLLs. They
have the limitation that the smallest possible frequency step is equal to
the reference frequency. This can be a problem for spread-spectrum
communications where transmission over a range of values in a narrow band
is required. The solution is a fractional-N PLL, which allows the
divider to be a non-integer number. This permits more precise control of
the output frequency. Fractional values are implemented by varying N
between two values. For example, to create N = 90.4, the sequence 90,
90, 90, 91, 91 would be used. One problem with this method however, is
that changes in the value of N result in an instantaneous phase change in
the output. This phase change creates spikes in the frequency spectrum
near the output frequency [5]. To overcome these limitations a deltasigma fractional-N PLL is needed. A delta-sigma PLL changes between N
values over a wider range. While unwanted noise is still created, it is
shifted to higher frequencies that are more easily filtered. It is even
possible to randomize the sequence of N values so that the noise is
spread out over the frequency spectrum. These functions are implemented
by a device called a delta-sigma modulator, which is used to create the
feedback divider[6].
In a digital PLL, the oscillator is controlled by an A/D converter
and the phase detector is replaced with a time to digital converter. A
time to digital converter is a device that gives the arrival time of a
waveform [7]. According to [8], Digital PLLs provide greater resistance
to noise, use less area, and are easier to port to new applications.
Implementing Phase Locked Loops
PLLs can be implemented using separate components for each building
block. Phase detectors and oscillators are both available from Digikey
[9]. However, the simplest and cheapest method of implementing a PLL is
with a single integrated circuit. PLL ics are available from Analog
Devices and range in price from $1.72 for a integer-N to $3.25 for a
fractional-N capable of subhertz resolution at 6Ghz [10].
[1]
Analog Devices, “Fiber Optic Receiver with Quantizer and Clock
Recovery and Data Retiming,” AD808 datasheet, Oct. 2006.
[2]
Analog Devices, “14-Output Clock Generator with Integrated 2.8 Ghz
VCO,” AD9516-0 datasheet, Apr. 2007.
[3]
Analog Devices, “AD6548 Othello-G Complete GSM/GPRS Transceiver,”
AD6548 datasheet, 2005.
[4]
D. Banerjee, PLL Performance, Simulation, and Design, 4th ed.
Indianapolis, IN: Dog Ear Publishing, 2006.
[5]
D. Foong, “Understanding Fractional-N PLL,” national.com, Dec.
2008. [Online]. Available:
http://www.national.com/CHS/AU/design/Fractional_N_PLL_2008/Fractional_N_
PLL_Eng.html. [Accessed Jan. 26, 2010].
[6]
D. Hillman, “Inherent Benefits of a Delta-Sigma Fractional-N PLL in
Power-Conscious Soc Designs,” chipdesignmag.com, para. 2, 2010. [Online].
Available: http://chipdesignmag.com/display.php?articleId=1030.
[Accessed Jan. 26, 2010].
[7]
M. Perrott, “Tutorial on Digital Phase-Locked Loops,” cppsim.com,
Sep. 2009. [Online]. Available:
http://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf.
[Accessed Jan. 26, 2010].
[8]
S. Mendel and C. Vogel, “A z-Domain Model and Analysis of PhaseDomain All-Digital Phase-Locked Loops,” In Proc. Norchip 2007, 2007, pp.
1-6.
[9]
“Product Index,” digikey.com, Jan. 26, 2010. [Online]. Available:
http://search.digikey.com/scripts/DkSearch/dksus.dll. [Accessed Jan. 26,
2010].
[10] “PLL Synthesizers/VCOs,” analog.com, 2010. [Online]. Available:
http://www.analog.com/en/clock-and-timing/pllsynthesizersvcos/products/index.html. [Accessed Jan. 26, 2010].