Latch
advertisement
MICROELETTRONICA Sequential circuits Lection 7 1 Outline • • • • • • • Floorplanning Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking 2 Project Strategy • Proposal – Specifies inputs, outputs, relation between them • Floorplan – Begins with block diagram – Annotate dimensions and location of each block – Requires detailed paper design • Schematic – Make paper design simulate correctly • Layout – Physical design, DRC, ERC 3 Floorplan • How do you estimate block areas? – Begin with block diagram – Each block has • • • • Inputs Outputs Function (draw schematic) Type: array, datapath, random logic • Estimation depends on type of logic 4 Area Estimation • Arrays: – Layout basic cell – Calculate core area from # of cells – Allow area for decoders, column circuitry • Datapaths – Sketch slice plan – Count area of cells from cell library – Ensure wiring is possible • Random logic – Evaluate complexity of the design you have done 5 Typical Layout Densities • • Typical numbers of high-quality layout Allocate space for big wiring channels Element Area Random logic (2 metal layers) 1000-1500 l2 / transistor Datapath 250 – 750 l2 / transistor SRAM 1000 l2 / bit DRAM 100 l2 / bit ROM 100 l2 / bit 6 Sequencing • Combinational logic – output depends on current inputs • Sequential logic – output depends on current and previous inputs – Requires separating previous, current, future – Called state or tokens – Ex: FSM, pipeline clk in clk clk clk out CL Finite State Machine CL CL Pipeline 7 Sequencing Cont. • If tokens moved through pipeline at constant speed, no sequencing elements would be necessary • Ex: fiber-optic cable – – – – Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses • This is called wave pipelining in circuits • In most circuits, dispersion is high – Delay fast tokens so they don’t catch slow ones. 8 Sequencing Overhead • Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. • Inevitably adds some delay to the slow tokens • Makes circuit slower than just the logic delay – Called sequencing overhead • Some people call this clocking overhead – But it applies to asynchronous circuits too – Inevitable side effect of maintaining sequence 9 Sequencing Elements clk D Flop Latch • Latch: Level sensitive – transparent latch, D latch • Flip-flop: edge triggered – master-slave flip-flop, D flip-flop, D register • Timing Diagrams clk – Transparent D Q – Opaque – Edge-trigger Q clk D Q (latch) Q (flop) 10 Latch Design • Pass Transistor Latch • Pros + Tiny + Low clock load • Cons – – – – – – Vt drop nonrestoring backdriving output noise sensitivity dynamic diffusion input D Q Used in 1970’s 11 Latch Design • Transmission gate + No Vt drop - Requires inverted clock Inverting buffer + Restoring + No backdriving + Fixes either • Output noise sensitivity • Or diffusion input Inverted output D Q X D Q D Q 12 Latch Design • Tristate feedback + Static – Backdriving risk X D Q • Static latches are now essential 13 Latch Design • Buffered output + No backdriving • Widely used in standard cells + Very robust (most important) - Rather large - Rather slow - High clock loading Q X D 14 Latch Design • Datapath latch + Smaller, faster - unbuffered input Q X D 15 Flip-Flop Design • Flip-flop is built as pair of back-to-back latches X D Q Q X D Q 16 Enable • Enable: ignore clock when en = 0 – Mux: increase latch D-Q delay – Clock Gating: increase en setup time, skew Symbol Multiplexer Design Clock Gating Design en D 1 Q 0 en Q D en 1 0 Q Flop D Q D en Flop Flop en Q en D Latch Latch D Latch Q 17 Reset • Force output low when reset asserted • Synchronous vs. asynchronous Q D reset Synchronous Reset Q reset D Q reset reset D Flop Symbol D Latch Q Q Asynchronous Reset Q Q reset reset D D reset reset 18 Set / Reset • Set forces output high when enabled • Flip-flop with asynchronous set and reset reset set D Q set reset 19 Sequencing Methods clk clk Flop clk Flop Combinational Logic tnonoverlap 2 Combinational Logic Half-Cycle 1 1 Combinational Logic Latch 1 Half-Cycle 1 tpw p Combinational Logic Latch p Latch Pulsed Latches p tnonoverlap Tc/2 2 Latch 2-Phase Transparent Latches 1 Latch Flip-Flops • Flip-flops • 2-Phase Latches • Pulsed Latches Tc 20 Timing Diagrams Contamination and Propagation Delays A Combinational Logic A tpd Y Y Logic Prop. Delay tcd Logic Cont. Delay tpcq Latch/Flop Clk-Q Prop Delay D tccq Latch/Flop Clk-Q Cont. Delay tpdq Latch D-Q Prop Delay clk clk Latch D-Q Cont. Delay Latch/Flop Setup Time thold D Q D tsetup Q tsetup tpcq Latch tpcq clk clk Flop tpd tcd tccq tsetup thold tccq tpcq Q D tcdq tpdq Q thold Latch/Flop Hold Time 21 clk sequencing overhead clk Q1 Combinational Logic D2 F2 t pd Tc tsetup t pcq F1 Max-Delay: Flip-Flops Tc clk Q1 tsetup tpcq tpd D2 22 Max Delay: 2-Phase Latches D1 sequencing overhead Q1 Combinational Logic 1 D2 1 Q2 Combinational Logic 2 D3 L3 pdq 2 L2 2t L1 t pd t pd 1 t pd 2 Tc 1 Q3 1 2 Tc D1 Q1 D2 Q2 tpdq1 tpd1 tpdq2 tpd2 D3 23 Max Delay: Pulsed Latches D1 sequencing overhead p Q1 D2 Combinational Logic L2 p L1 t pd Tc max t pdq , t pcq tsetup t pw Q2 Tc D1 (a) tpw > tsetup tpdq Q1 tpd D2 p tpcq Q1 Tc tpd tpw tsetup (b) tpw < tsetup D2 24 Min-Delay: Flip-Flops clk F1 tcd thold tccq Q1 CL clk F2 D2 clk Q1 tccq D2 tcd thold 25 Min-Delay: 2-Phase Latches 1 L1 tcd 1,tcd 2 thold tccq tnonoverlap Q1 CL Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! D2 1 L2 2 tnonoverlap tccq 2 Q1 D2 tcd thold 26 Min-Delay: Pulsed Latches p L1 tcd thold tccq t pw Q1 CL D2 Hold time increased by pulse width p L2 p tpw thold Q1 tccq tcd D2 27 Time Borrowing • In a flop-based system: – – – – – Data launches on a rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges • In a latch-based system – Data can pass through latch while transparent – Long cycle of logic can borrow time into next – As long as each loop completes in one cycle 28 Time Borrowing Example 1 2 Combinational Logic Borrowing time across half-cycle boundary Combinational Logic Borrowing time across pipeline stage boundary 2 Combinational Logic Latch (b) Latch 1 1 Latch 2 Latch (a) Latch 1 Combinational Logic Loops may borrow time internally but must complete within the cycle 29 How Much Borrowing? 2-Phase Latches Tc tsetup tnonoverlap 2 D1 2 Q1 Combinational Logic 1 D2 L2 tborrow L1 1 Q2 1 Pulsed Latches 2 tborrow t pw tsetup tnonoverlap Tc Tc/2 Nominal Half-Cycle 1 Delay tborrow tsetup D2 30 Clock Skew • We have assumed zero clock skew • Clocks really have uncertainty in arrival time – Decreases maximum propagation delay – Increases minimum contamination delay – Decreases time borrowing 31 Skew: Flip-Flops Combinational Logic D2 Tc clk tcd thold tccq tskew tpcq Q1 tskew tpdq tsetup D2 F1 clk Q1 CL clk D2 F2 sequencing overhead Q1 F1 t pd Tc t pcq tsetup tskew clk F2 clk tskew clk thold Q1 tccq D2 tcd 32 Skew: Latches pdq sequencing overhead tcd 1 , tcd 2 thold tccq tnonoverlap tskew tborrow D1 2 Q1 Combinational Logic 1 D2 1 Q2 Combinational Logic 2 D3 L3 2t L1 t pd Tc 1 L2 2-Phase Latches Q3 1 2 Tc tsetup tnonoverlap tskew 2 Pulsed Latches t pd Tc max t pdq , t pcq tsetup t pw tskew sequencing overhead tcd thold t pw tccq tskew tborrow t pw tsetup tskew 33 Two-Phase Clocking • If setup times are violated, reduce clock speed • If hold times are violated, chip fails at any speed • An easy way to guarantee hold times is to use 2phase latches with big nonoverlap times • Call these clocks 1, 2 (ph1, ph2) 34 Safe Flip-Flop • It’s possible to use flip-flop with nonoverlapping clocks – Very slow – nonoverlap adds to setup time – But no hold times • In industry, use a better timing analyzer – Add buffers to slow signals if hold time is at risk Q X D Q 35 Summary • 2-Phase Transparent Latches: – Lots of skew tolerance and time borrowing • Flip-Flops: – Very easy to use, supported by all tools • Pulsed Latches: – Fast, some skew tol & borrow, hold time risk 36
