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Logic Circuits
Combinational
Circuits
Sequential
Circuits
•Consists of logic gates
whose outputs are
determined from the
current combination of
inputs.
•Employ storage elements
in addition to logic gates.
•Performs an operation
that can be specified by a
set of Boolean functions.
•Output depend on present
value of input + past input.
•Outputs are a function of
the inputs and the state of
the storage elements.
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
Storage Elements and Analysis
◦ Introduction to sequential circuits
◦ Types of sequential circuits
◦ Storage elements
 Latches
 Flip-flops
◦ Sequential circuit analysis
 State tables
 State diagrams
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Inputs

A Sequential
circuit contains: Storage
◦ Storage elements: Elements
Latches or Flip-Flops
◦ Combinatorial Logic:
Combinational
Logic
 Implements a multiple-output State
switching function
 Inputs are signals from the outside.
 Outputs are signals to the outside.
 Other inputs, State or Present State,
are signals from storage elements.
 The remaining outputs, Next State are
inputs to storage elements.
Outputs
Next
State
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Inputs
Outputs
Combinational
Logic
Storage
Elements
State
Next
State
 Sequential Logic
◦ Output function
Outputs = g(Inputs, State)
◦ Next state function
Next State = f(Inputs, State)
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


Depends on the times at which:
◦ storage elements observe their inputs, and
◦ storage elements change their state
Synchronous
◦ Behavior defined from knowledge of its signals at discrete
instances of time
◦ Storage elements observe inputs and can change state
only in relation to a timing signal (clock pulses from a
clock)
Asynchronous
◦ Behavior defined from knowledge of inputs at any instant
of time and the order in continuous time in which inputs
change
◦ If clock just regarded as another input, all circuits are
asynchronous!
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




Storage elements
 Maintain a binary state (0 or 1) indefinitely as
long as power is delivered to the circuit
 Switch states (01 or 10) when directed by
an input signal
Most basic storage element
Used mainly to construct Flip-Flops
Asynchronous storage circuit
Types of latches:
◦ SR Latches
◦ S`R` Latches
◦ D Latches
X=X
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
Cross-coupling two
NOR gates gives the
S – R Latch:
R (reset)
S (set)
S
R
Q
Q’
COMMENTS
0
0
?
?
Undefined state
1
0
1
0
Set
0
0
1
0
After S=1,R=0
0
1
0
1
Reset
0
0
0
1
After S=0,R=1
1
1
0
0
forbidden
0
0
?
?
Undefined state
Q
Q
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
“Cross-Coupling”
two NAND gates gives
the S -R Latch:
S (set)
R (reset)
S
R
Q
Q’
COMMENTS
1
1
?
?
Undefined state
1
0
0
1
set
1
1
0
1
After S=1,R=0
0
1
1
0
reset
1
1
1
0
After S=0,R=1
0
0
1
1
forbidden
1
1
?
?
Undefined state
Q
Q
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
Adding two NAND
gates to the basic
S - R NAND latch
gives the clocked
S – R latch:
S`
S
Q
1
C
1


Has a time sequence R
behavior similar to the
basic S-R latch except that
the S and R inputs are only
observed when the line C
is high.
C means “control” or
“clock”.
R`
Q
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

Adding an inverter
to the S-R Latch,
gives the D Latch:
Note that there are
no “indeterminate”
states!
Q
0
0
1
1
D
0
1
0
1
Q(t+1)
0
1
0
1
D
Q
C
Comment
No change
Set Q
Clear Q
No Change
Q
The graphic symbol for a
D Latch is:
D
Q
C
Q
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S
Q
S
Q
D
Q
R
Q
R
Q
C
Q
SR
S’R’
D
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Chapter 5: Sequential Circuits
5.4: Flip-Flops
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



The latch timing problem
Master-slave flip-flop
Edge-triggered flip-flop
Other flip-flops
- JK flip-flop
- T flip-flop
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
In a sequential circuit, paths may exist through
combinational logic:
◦ From one storage element to another
◦ From a storage element back to the same storage
element


The combinational logic between a latch output and
a latch input may be as simple as an interconnect
For a clocked D-latch, the output Q depends on the
input D whenever the clock input C has value 1
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

Consider the following circuit:
Suppose that initially Y = 0.
Clock
D
Q
C
Q
Y
Clock
Y




As long as C = 1, the value of Y continues to change!
The changes are based on the delay present on the loop
through the connection from Y back to Y.
This behavior is clearly unacceptable.
Desired behavior: Y changes only once per clock pulse
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

A solution to the latch timing problem is to
break the closed path from Y to Y within the
storage element
The commonly-used, path-breaking
solutions replace the clocked D-latch with:
◦ a master-slave flip-flop
◦ an edge-triggered flip-flop
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Master
D





D
Y
Slave
D
Q
Consists of two clocked
C
C
C
D latches in series
with the clock on the
second latch inverted
The input is observed
by the first latch with C = 1
The output is changed by the second latch with C = 0
The path from input to output is broken by the
difference in clocking values (C = 1 and C = 0).
The behavior demonstrated by the example with D
driven by Y given previously is prevented since the
clock must change from 1 to 0 before a change in Y
based on D can occur.
Q
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