VHDL Examples
Subra Ganesan
Reference: Professor Haskell’s Notes,
Digital design with VHDL book by Vranesic
n-line 2-to-1 Multiplexer
a(n-1:0)
b(n-1:0)
n-line
2 x 1 MUX
sel
y(n-1:0)
sel y
0 a
1 b
2
An n-line 2 x 1 MUX
a(n-1:0)
library IEEE;
use IEEE.std_logic_1164.all;
b(n-1:0)
n-line
2x1
MUX
y(n-1:0)
entity mux2g is
sel
generic (width:positive);
port (
a: in STD_LOGIC_VECTOR(width-1 downto 0);
b: in STD_LOGIC_VECTOR(width-1 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(width-1 downto 0)
);
end mux2g;
3
Entity
library IEEE;
use IEEE.std_logic_1164.all;
Each entity must
begin with these
library and use
statements
generic statement defines
width of bus
entity mux2g is
generic (width:positive);
port (
a: in STD_LOGIC_VECTOR(width-1 downto 0);
b: in STD_LOGIC_VECTOR(width-1 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(width-1 downto 0)
);
end mux2g;
port statement defines
inputs and outputs
4
Entity
library IEEE;
use IEEE.std_logic_1164.all;
Mode: in or out
entity mux2g is
generic (width:positive);
port (
a: in STD_LOGIC_VECTOR(width-1 downto 0);
b: in STD_LOGIC_VECTOR(width-1 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(width-1 downto 0)
);
end mux2g;
Data type: STD_LOGIC,
STD_LOGIC_VECTOR(width-1 downto 0);
5
Standard Logic
library IEEE;
use IEEE.std_logic_1164.all;
type std_ulogic is ( ‘U’, -- Uninitialized
‘X’ -- Forcing unknown
‘0’ -- Forcing zero
‘1’ -- Forcing one
‘Z’ -- High impedance
‘W’ -- Weak unknown
‘L’ -- Weak zero
‘H’ -- Weak one
‘-’); -- Don’t care
6
Standard Logic
Type std_ulogic is unresolved.
Resolved signals provide a mechanism
for handling the problem of multiple
output signals connected to one signal.
subtype std_logic is resolved std_ulogic;
7
Architecture
architecture mux2g_arch of mux2g is
begin
mux2_1: process(a, b, sel)
begin
a(n-1:0)
if sel = '0' then
y <= a;
else
b(n-1:0)
y <= b;
end if;
end process mux2_1;
end mux2g_arch;
n-line
2x1
MUX
y(n-1:0)
sel
Note: <= is signal assignment
8
Architecture
entity name
process sensitivity
list
architecture mux2g_arch of mux2g is
begin
mux2_1: process(a, b, sel)
begin
Sequential statements
if sel = '0' then
y <= a;
(if…then…else) must be
else
in a process
y <= b;
end if;
end process mux2_1;
end mux2g_arch;
Note begin…end
in architecture
Note begin…end
in process
9
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
Top-level design
for Lab 1
entity Lab1 is
port(
SW : in STD_LOGIC_VECTOR(7 downto 0);
BTN0 : in STD_LOGIC;
LD : out STD_LOGIC_VECTOR(3 downto 0)
);
end Lab1;
SW(7:4)
SW(3:0)
a 4-line
2-to-1
b MUX
y
LD(3:0)
sel
BTN0
10
architecture Lab1_arch of Lab1 is
component mux2g
generic(
width : POSITIVE);
port(
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
sel : in std_logic;
y : out std_logic_vector((width-1) downto 0));
end component;
constant bus_width: integer := 4;
begin
mux2: mux2g generic map(width => bus_width) port map
(a => SW(7 downto 4),b => SW(3 downto 0), sel => BTN0, y => LD);
end Lab1_arch;
SW(7:4)
SW(3:0)
a 4-line
2-to-1
b MUX
y
LD(3:0)
sel
BTN0
11
Example of case statement
architecture mux4g_arch of mux4g is
begin
process (sel, a, b, c, d)
begin
case sel is
when "00"
=> y <= a;
when "01"
=> y <= b;
when "10"
=> y <= c;
when others => y <= d;
end case;
end process;
end mux4g_arch;
Note implies operator =>
Sel
“00”
“01”
“10”
“11”
y
a
b
c
d
Must include ALL possibilities
in case statement
12
7-Segment Display
D(3:0)
Truth table
D
0
1
2
3
4
5
6
7
a
1
0
1
1
0
1
1
1
b
1
1
1
1
1
0
0
1
c
1
1
0
1
1
1
1
1
d
1
0
1
1
0
1
1
0
e
1
0
1
0
0
0
1
0
f
1
0
0
0
1
1
1
0
g
0
0
1
1
1
1
1
0
D
8
9
A
b
C
d
E
F
a
1
1
1
0
1
0
1
1
b
1
1
1
0
0
1
0
0
c
1
1
1
1
0
1
0
0
d
1
1
0
1
1
1
1
0
seg7dec
e
1
0
1
1
1
1
1
1
f
1
1
1
1
1
0
1
1
AtoG(6:0)
g
1
1
1
1
0
1
1
1
13
7-Segment Display
Verilog
Behavior
D(3:0)
seg7dec
case(D)
0: AtoG =
1: AtoG =
2: AtoG =
3: AtoG =
4: AtoG =
5: AtoG =
6: AtoG =
7: AtoG =
8: AtoG =
9: AtoG =
'hA: AtoG =
'hb: AtoG =
'hC: AtoG =
'hd: AtoG =
AtoG(6:0) 'hE: AtoG =
'hF: AtoG =
default: AtoG
endcase
7'b1111110;
7'b0110000;
7'b1101101;
7'b1111001;
7'b0110011;
7'b1011011;
7'b1011111;
7'b1110000;
7'b1111111;
7'b1111011;
7'b1110111;
7'b0011111;
7'b1001110;
7'b0111101;
7'b1001111;
7'b1000111;
= 7'b1111110;
// 0
14
7-Segment Display
VHDL
-- seg7dec
with digit select
ssg <= "1001111" when
"0010010" when
"0000110" when
AtoG
"1001100" when
"0100100" when
"0100000" when
"0001111" when
"0000000" when
"0000100" when
"0001000" when
"1100000" when
"0110001" when
"1000010" when
sseg(6:0)
seg7dec
"0110000" when
"0111000" when
"0000001" when
Behavior
(Active LOW)
digit(3:0)
"0001", --1
"0010", --2
"0011", --3
"0100", --4
"0101", --5
"0110", --6
"0111", --7
"1000", --8
"1001", --9
"1010", --A
"1011", --b
"1100", --C
"1101", --d
"1110", --E
"1111", --F
others; --0
15
Comparators
Recall that an XNOR gate can
be used as an equality detector
XNOR
X
Y
Z = !(X $ Y)
Z = X xnor Y
Z = ~(X @ Y)
Z
if X = Y then
Z <= '1';
else
Z <= '0';
end if;
X
0
0
1
1
Y
0
1
0
1
Z
1
0
0
1
16
4-Bit Equality Comparator
A0
A1
A2
A3
B0
B1
C0
C1
B2
C2
B3
C3
A_EQ_B
A: in STD_LOGIC_VECTOR(3 downto 0);
B: in STD_LOGIC_VECTOR(3 downto 0);
A_EQ_B: out STD_LOGIC;
17
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
A0
A1
A2
B0
B1
B2
C0
C1
A_EQ_B
C2
A3
B3
entity eqdet4 is
C3
Port ( A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
A_EQ_B : out std_logic);
end eqdet4;
architecture Behavioral of eqdet4 is
signal C: std_logic_vector(3 downto 0);
begin
C <= A xnor B;
A_EQ_B <= C(0) and C(1) and C(2) and C(3);
end Behavioral;
18
Comparators
A_EQ_B
A(n-1:0)
A_GT_B
comp
B(n-1:0)
A_LT_B
A_UGT_B
A_ULT_B
A, B
signed
A, B
unsigned
Signed: 2's complement signed numbers
19
-- Comparator for unsigned and signed numbers
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
A(n-1:0)
comp
B(n-1:0)
A_EQ_B
A_GT_B
A_LT_B
A_UGT_B
A_ULT_B
entity comp is
generic(width:positive);
port (
A: in STD_LOGIC_VECTOR(width-1 downto 0);
B: in STD_LOGIC_VECTOR(width-1 downto 0);
A_EQ_B: out STD_LOGIC;
A_GT_B: out STD_LOGIC;
A_LT_B: out STD_LOGIC;
A_ULT_B: out STD_LOGIC;
A_UGT_B: out STD_LOGIC
);
end comp;
20
architecture comp_arch of comp is
begin
CMP: process(A,B)
variable AVS, BVS: signed(width-1 downto 0);
begin
for i in 0 to width-1 loop
AVS(i) := A(i);
BVS(i) := B(i);
end loop;
A_EQ_B <= '0';
A(n-1:0)
A_GT_B <= '0';
A_LT_B <= '0';
B(n-1:0)
A_ULT_B <= '0';
A_UGT_B <= '0';
if (A = B) then
A_EQ_B <= '1';
end if;
if (AVS > BVS) then
A_GT_B <= '1';
end if;
if (AVS < BVS) then
A_LT_B <= '1';
end if;
if (A > B) then
A_UGT_B <= '1';
end if;
if (A < B) then
A_ULT_B <= '1';
end if;
end process CMP;
end comp_arch;
comp
A_EQ_B
A_GT_B
A_LT_B
A_UGT_B
A_ULT_B
Note: All outputs must be
assigned some value.
The last signal assignment
in a process is the value assigned
21
4-Bit Comparator
22
Full Adder
Truth table
Ci Ai Bi Si Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Ci
Ai
Bi
Combinational
Logic
Si
Ci+1
Behavior
Ci+1:Si = Ci + Ai + Bi
23
Full Adder
Ai
C i+1
Bi
Full Adder
Ci
Si
Block Diagram
24
4-Bit Adder
A3
B3
A2
Full Adder
Full Adder
4
S3
B1
S
1
0 1
0 0
1 0
B0
Full Adder
C0
C1
S2
C
0:A
0:B
C4:S
A0
Full Adder
C2
C3
C
A1
B2
1
1
1
1
S
1
1
0
1
0
0
0
0
1
1
0
25
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity adder4 is
port(
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
carry : out STD_LOGIC;
S : out STD_LOGIC_VECTOR(3 downto 0)
);
end adder4;
architecture adder4 of adder4 is
begin
process(A,B)
variable temp: STD_LOGIC_VECTOR(4 downto 0);
begin
temp := ('0' & A) + ('0' & B);
S <= temp(3 downto 0);
carry <= temp(4);
end process;
end adder4;
26
4-Bit Adder
27
3-to-8 Decoder
A: in STD_LOGIC_VECTOR(2 downto 0);
Y: out STD_LOGIC_VECTOR(0 to 7);
Behavior
for i in 0 to 7 loop
if(i = conv_integer(A))
Y(i) <= ‘1’;
A2
else
0
Y(i) <= ‘0’;
0
end if;
0
end loop;
0
1
1
1
1
then
A1 A0
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
28
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
3-to-8 Decoder
entity decode38 is
port(
A : in STD_LOGIC_VECTOR(2 downto 0);
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end decode38;
architecture decode38 of decode38 is
begin
process(A)
variable j: integer;
begin
j := conv_integer(A);
for i in 0 to 7 loop
if(i = j) then
Y(i) <= '1';
else
Y(i) <= '0';
end if;
end loop;
end process;
end decode38;
29
Shifters
D3
s1
D2
D1
D0
Shifter
s0
s1
0
0
1
1
s0
0
1
0
1
noshift
U2/
2*
2/
Y3
Y2
Y1
Y0
D3
0
D2
D3
D2
D3
D1
D3
D1
D2
D0
D2
D0
D1
0
D1
Shift right
Shift left
Arithmetic shift right
30
shift4.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
D3
s1
D2
D1
D0
Shifter
s0
entity shifter is
Y3 Y2
generic(width:positive := 4);
port (
D: in STD_LOGIC_VECTOR(width-1 downto 0);
s: in STD_LOGIC_VECTOR(1 downto 0);
Y: out STD_LOGIC_VECTOR(width-1 downto 0)
);
end shifter;
Y1
Y0
31
architecture shifter_arch of shifter is
begin
shift_1: process(D, s)
begin
case s is
when "00" =>
-- no shift
Y <= D;
when "01" =>
-- U2/
Y <= '0' & D(width-1 downto 1);
when "10" =>
-- 2*
Y <= D(width-2 downto 0) & '0';
when "11" =>
-- 2/
Y <= D(width-1) & D(width-1 downto 1);
when others =>
Y <= D;
end case;
end process shift_1;
end shifter_arch;
-- no shift
32
Code Converters
• Gray Code Converter
• Binary-to-BCD Converter
33
Gray Code
Definition: An ordering of 2n binary numbers such that
only one bit changes from one entry to the next.
Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}
Gray coding {0...7}:
{000, 001, 011, 010, 110, 111, 101, 100}
Not unique
One method for generating a Gray code sequence:
Start with all bits zero and successively flip the
right-most bit that produces a new string.
34
Binary - Gray Code Conversions
Gray code: G(i), i = n – 1 downto 0
Binary code: B(i), i = n – 1 downto 0
Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}
Gray coding {0...7}:
{000, 001, 011, 010, 110, 111, 101, 100}
Convert Binary to Gray:
Copy the most significant bit.
For each smaller i
G(i) = B(i+1) xor B(i)
Convert Gray to Binary:
Copy the most significant bit.
For each smaller i
B(i) = B(i+1) xor G(i)
35
library IEEE;
use IEEE.STD_LOGIC_1164.all;
bin2gray.vhd
entity bin2gray is
generic(width:positive := 3);
port(
B : in STD_LOGIC_VECTOR(width-1 downto 0);
G : out STD_LOGIC_VECTOR(width-1 downto 0)
);
end bin2gray;
architecture bin2gray of bin2gray is
begin
process(B)
begin
G(width-1) <= B(width-1);
for i in width-2 downto 0 loop
G(i) <= B(i+1) xor B(i);
end loop;
end process;
end bin2gray;
36
library IEEE;
use IEEE.STD_LOGIC_1164.all;
gray2bin.vhd
entity gray2bin is
generic(width:positive := 3);
port(
G : in STD_LOGIC_VECTOR(width-1 downto 0);
B : out STD_LOGIC_VECTOR(width-1 downto 0)
);
end gray2bin;
architecture gray2bin of gray2bin is
begin
process(G)
variable BV: STD_LOGIC_VECTOR(width-1 downto 0);
begin
BV(width-1) := G(width-1);
for i in width-2 downto 0 loop
BV(i) := BV(i+1) xor G(i);
end loop;
B <= BV;
end process;
end gray2bin;
37
Binary-to-BCD Conversion
• Shift and add 3 algorithm
• RTL solution
• Behavioral solution
38
Shift and Add-3 Algorithm
11.
22.
33.
44.
Shift the binary number left one bit.
If 8 shifts have taken place, the BCD number is in the
Hundreds, Tens, and Units column.
If the binary value in any of the BCD columns is 5 or greater,
add 3 to that value in that BCD column.
Go to 1.
Operation
HEX
Start
Hundreds
Tens
Units
Binary
F
1 1 1 1
F
1 1 1 1
39
Steps to convert an 8-bit binary number to BCD
Operation
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
Add 3
Shift 7
Add 3
Shift 8
BCD
P
z
Hundreds
Tens
Units
Binary
4
3
7
1
1
1 0
2
9 8
17 16
1
0
0
0
7
15
1
1 1
0 0
0 1
0 1
1 0
5
1
1
1
0
1
0
0
1
1
0
1
0
0
0
0
1
0
4
12
3
11
1
1 1
0 1
1 0
0 0
0 0
0 1
0 1
1 1
0 1
1 0
5
1
1
1
0
1
0
1
1
1
1
0
1
0
8
1
1
1
1
1
1
1
1
1
1
1
1
7
F
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
1
1
1
1
1
1
1
1
4
0
F
1 1 1 1
1 1 1
1 1
1
1
3
0
40
Truth table for Add-3 Module
A3 A2 A1 A0
C
S3 S2 S1 S0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S3
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
S2
0
0
0
0
1
0
0
0
0
1
X
X
X
X
X
X
S1
0
0
1
1
0
0
0
1
1
0
X
X
X
X
X
X
S0
0
1
0
1
0
0
1
0
1
0
X
X
X
X
X
X
41
Binary-to-BCD
Converter
RTL Solution
42
Binary-to-BCD Converter: Behavioral Solution
-- Title: Binary-to-BCD Converter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity binbcd is
port (
B: in STD_LOGIC_VECTOR (7 downto 0);
P: out STD_LOGIC_VECTOR (9 downto 0)
);
end binbcd;
43
architecture binbcd_arch of binbcd is
begin
Operation
bcd1: process(B)
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
Add 3
Shift 7
Add 3
Shift 8
BCD
P
z
Hundreds
Tens
Units
variable z: STD_LOGIC_VECTOR (17 downto 0);
begin
for i in 0 to 17 loop
z(i) := '0';
end loop;
z(10 downto 3) := B;
Binary
4
3
7
1
1
1 0
2
9
8
1
0
0
0
7
1
1 1
0 0
0 1
0 1
1 0
5
1
1
1
0
1
0
0
1
1
0
1
0
0
0
0
1
0
4
3
1
0
1
0
0
0
0
1
0
1
1
1
1
0
0
0
1
1
1
1
0
5
1
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
F
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
1
1
1
1
1
1
1
1
0
F
1 1 1 1
1 1 1
1 1
1
1
0
17 16 15
12 11
8 7
4
3
for i in 0 to 4 loop
if z(11 downto 8) > 4 then
z(11 downto 8) := z(11 downto 8) + 3;
end if;
if z(15 downto 12) > 4 then
z(15 downto 12) := z(15 downto 12) + 3;
end if;
z(17 downto 1) := z(16 downto 0);
end loop;
P <= z(17 downto 8);
end process bcd1;
end binbcd_arch;
44
0
16-bit
Binary-to-BCD
Converter
45
Verilog binbcd
module binbcd(B,P);
input [15:0] B;
output [15:0] P;
reg [15:0] P;
reg [31:0] z;
integer i;
46
always @(B)
begin
for(i = 0; i <= 31; i = i+1)
z[i] = 0;
z[18:3] = B;
for(i = 0; i <= 12; i = i+1)
begin
if(z[19:16] > 4)
z[19:16] = z[19:16]
if(z[23:20] > 4)
z[23:20] = z[23:20]
if(z[27:24] > 4)
z[27:24] = z[27:24]
if(z[31:28] > 4)
z[31:28] = z[31:28]
z[31:1] = z[30:0];
end
P = z[31:16];
end
endmodule
+ 3;
+ 3;
+ 3;
+ 3;
47
Arithmetic Logic Units
• ALU1
– Shifting, Increment and Decrement Instructions
• ALU2
– Arithmetic and Logic Instructions
• ALU3
– Comparators
48
ALU1
Shifting, Increment and Decrement Instructions
a(n-1:0)
n-line
ALU1
y(n-1:0)
Sel(2:0)
Sel
y
Name
'000'
a+1
1+
'001'
a-1
1-
'010'
not a
invert
'011'
LSL a
2*
'100'
LSR a
U2/
'101'
ASR a
2/
'110'
All ones
true
'111'
All zeros
false
49
alu1.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu1 is
generic(width:positive);
port (
a: in STD_LOGIC_VECTOR(width-1 downto 0);
sel: in STD_LOGIC_VECTOR(2 downto 0);
y: out STD_LOGIC_VECTOR(width-1 downto 0)
);
end alu1;
a(n-1:0)
n-line
ALU1
y(n-1:0)
Sel(2:0)
50
architecture alu1_arch of alu1 is
begin
alu_1: process(a, sel)
variable true, false: STD_LOGIC_VECTOR (width-1 downto 0);
begin
-- true is all ones; false is all zeros
for i in 0 to width-1 loop
true(i) := '1';
false(i) := '0';
end loop;
case sel is
when "000" =>
-- 1+
y <= a + 1;
when "001" =>
-- 1y <= a - 1;
when "010" =>
-- invert
y <= not a;
when "011" =>
-- 2*
y <= a(width-2 downto 0) & '0';
when "100" =>
-- U2/
y <= '0' & a(width-1 downto 1);
when "101" =>
-- 2/
y <= a(width-1) & a(width-1 downto 1);
when "110" =>
-- TRUE
y <= true;
when others =>
-- FALSE
y <= false;
end case;
end process alu_1;
end alu1_arch;
51
ALU2
Arithmetic and Logic Instructions
a(n-1:0)
n-line
ALU2
y(n-1:0)
b(n-1:0)
Sel
y
Name
'000'
a+b
+
'001'
b-a
-
'010'
a and b
AND
'011'
a or b
OR
'100'
a xor b
XOR
'101'
true if a = 0
false otherwise
0=
'110'
true if a < 0
false otherwise
0<
'111'
true if b > a
false otherwise
U>
sel(2:0)
52
alu2.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu2 is
generic(width:positive);
port (
a: in STD_LOGIC_VECTOR(width-1 downto 0);
b: in STD_LOGIC_VECTOR(width-1 downto 0);
sel: in STD_LOGIC_VECTOR(2 downto 0);
y: out STD_LOGIC_VECTOR(width-1 downto 0)
);
end alu2;
a(n-1:0)
n-line
ALU2
y(n-1:0)
b(n-1:0)
sel(2:0)
53
architecture alu2_arch of alu2 is
begin
alu_2: process(a, b, sel)
variable true, false: STD_LOGIC_VECTOR (width-1 downto 0);
variable Z: STD_LOGIC;
begin
Z := '0';
for i in 0 to width-1 loop
true(i) := '1';
-- true is all ones;
false(i) := '0';
-- false is all zeros
Z := Z or a(i);
-- Z = '0' if all a(i) = '0'
end loop;
case sel is
when "000" =>
y <= a + b;
-- +
when "001" =>
y <= b - a;
-- -
when "010" =>
y <= a and b;
-- AND
when "011" =>
y <= a or b;
-- OR
when "100" =>
y <= A xor B;
-- XOR
54
when "101"
if (Z =
y <=
else
y <=
end if;
=>
'0') then
true;
-- 0=
NOT
false;
when "110" =>
-- 0<
if (a(width-1) = '1') then
y <= true;
else
y <= false;
end if;
when "111"
if (b >
y <=
else
y <=
end if;
=>
a) then
true;
-- U>
false;
when others =>
null;
end case;
end process alu_2;
end alu2_arch;
55
ALU3
Comparators
a(n-1:0)
n-line
ALU3
y(n-1:0)
b(n-1:0)
Sel
y
Name
'000'
true if b = a
false otherwise
=
'001'
true if b /= a
false otherwise
<>
'010'
true if b < a (unsigned)
false otherwise
U<
'011'
true if b > a (unsigned)
false otherwise
U>
'100'
true if b <= a (unsigned)
false otherwise
U<=
'101'
true if b < a (signed)
false otherwise
<
'110'
true if b > a (signed)
false otherwise
>
'111'
true if b <= a (signed)
false otherwise
<=
sel(2:0)
56
alu3.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity alu3 is
generic(width:positive);
port (
a: in STD_LOGIC_VECTOR(width-1 downto 0);
b: in STD_LOGIC_VECTOR(width-1 downto 0);
sel: in STD_LOGIC_VECTOR(2 downto 0);
y: out STD_LOGIC_VECTOR(width-1 downto 0)
);
end alu3;
a(n-1:0)
n-line
ALU3
y(n-1:0)
b(n-1:0)
sel(2:0)
57
architecture alu3_arch of alu3 is
begin
alu_3: process(a, b, sel)
variable true, false: STD_LOGIC_VECTOR (width-1 downto 0);
variable avs, bvs: signed(width-1 downto 0);
begin
for i in 0 to width-1 loop
true(i) := '1'; -- true is all ones;
false(i) := '0'; -- false is all zeros
avs(i) := a(i);
bvs(i) := b(i);
end loop;
case sel is
when "000" =>
if (a = b) then
y <= true;
else
y <= false;
end if;
-- =
58
when "001" =>
if (a /= b) then
y <= true;
else
y <= false;
end if;
-- <>
when "010" =>
if (b < a) then
y <= true;
else
y <= false;
end if;
-- U<
when "011" =>
if (b > a) then
y <= true;
else
y <= false;
end if;
-- U>
when "100" =>
if (b <= a) then
y <= true;
else
y <= false;
end if;
-- U<=
59
when "101" =>
if (bvs < avs) then
y <= true;
else
y <= false;
end if;
-- <
when "110" =>
if (bvs > avs) then
y <= true;
else
y <= false;
end if;
-- >
when "111" =>
if (bvs <= avs) then
y <= true;
else
y <= false;
end if;
-- <=
when others =>
null;
end case;
end process alu_3;
end alu3_arch;
60
ROM
addr(2:0)
0
1
2
3
4
5
6
7
85
C4
E6
55
67
D4
F4
C6
M(7:0)
61
ROM.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ROM is
port (
addr: in STD_LOGIC_VECTOR (2 downto 0);
M: out STD_LOGIC_VECTOR (7 downto 0)
);
end ROM;
addr(2:0)
0
1
2
3
4
5
6
7
85
C4
E6
55
67
D4
F4
C6
M(7:0)
62
architecture ROM_arch of ROM is
constant data0: STD_LOGIC_VECTOR
constant data1: STD_LOGIC_VECTOR
constant data2: STD_LOGIC_VECTOR
constant data3: STD_LOGIC_VECTOR
constant data4: STD_LOGIC_VECTOR
constant data5: STD_LOGIC_VECTOR
constant data6: STD_LOGIC_VECTOR
constant data7: STD_LOGIC_VECTOR
(7
(7
(7
(7
(7
(7
(7
(7
downto
downto
downto
downto
downto
downto
downto
downto
0)
0)
0)
0)
0)
0)
0)
0)
:=
:=
:=
:=
:=
:=
:=
:=
"10000101";
"11000100";
X"E6";
X"55";
X"67";
X"D4";
"11110100";
"11000110";
type rom_array is array (NATURAL range <>) of STD_LOGIC_VECTOR (7 downto 0);
constant rom: rom_array := (
data0, data1, data2, data3,
data4, data5, data6, data7
);
begin
0
85
process(addr)
1
variable j: integer;
C4
begin
2
E6
j := conv_integer(addr);
3
55
addr(2:0)
M(7:0)
M <= rom(j);
4
67
end process;
5
D4
end ROM_arch;
6
7
F4
C6
63
architecture alu3_arch of alu3 is
begin
alu_3: process(a, b, sel)
variable true, false: STD_LOGIC_VECTOR (width-1 downto 0);
variable avs, bvs: signed(width-1 downto 0);
begin
for i in 0 to width-1 loop
true(i) := '1'; -- true is all ones;
false(i) := '0'; -- false is all zeros
avs(i) := a(i);
bvs(i) := b(i);
end loop;
case sel is
when "000" =>
if (a = b) then
y <= true;
else
y <= false;
end if;
-- =
64