Thermal Noise in n-Channel s-Si MOSFETs
Noise in strained-Si MOSFET
for low-power applications
K. Fobelets1 and J.E. Velázquez2
____________________________________________
1Dept.
of Electrical and Electronic Engineering, Imperial College, London, UK
2Dept.
de Física Aplicada - Universidad de Salamanca
Universidad de Salamanca
Thermal Noise in n-Channel s-Si MOSFETs
Motivation
Traditionally the improvement of circuit performance in CMOS
has been achieved by shifting to the next technology node. But,
shrinking under 100-nm, leads to
• Higher fields + Higher channel doping = Mobility degradation
• Leakage currents
= Thermal challenges → Interest of low-power
• Increased costs at each new node: Inexorable reduction of ROI
Outcome: Need for performance improvement at the device level
in each future technological node
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Thermal Noise in n-Channel s-Si MOSFETs
Motivation
Non-optimized BC SiGe MODFET
nearly matches 90-nm CMOS
performance at low-power!!!
K. Fobelets, W. Jeamsaksiri, C. Papavasilliou, T. Vilches, V. Gaspari,
J.E. Velazquez-Perez, K. Michelakis, T. Hackbarth, U. König
“Comparison of sub-micron Si:SiGe heterojunction nFETs to Si
nMOSFET in present-day technologies”, Solid-State Electronics 48
(2004) 1401–1406
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Thermal Noise in n-Channel s-Si MOSFETs
Presentation Outline
1. SS n-channel FETs
2. Device Under Study & Description of the
simulation
3. DC and RF results
4. Noise Behaviour
5. Conclusions
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Thermal Noise in n-Channel s-Si MOSFETs
Introduction
• Si/SiGe FET technologies will improve analog circuits:
Expected cost iii than III-V (Si wafers!?)
Native CMOS (p-channel or both)
SOI way exists!
Promising low-power performances
Mismatches impact @ a frequency given is iii if m
increases :
 I D  / I D WLeff
• Still a lack of widely established models, measurements, Spice
equivalent circuits… and noise analysis
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Thermal Noise in n-Channel s-Si MOSFETs
Two main ways for SC SS MOSFETs
• Si strained n-channel on a
SiGe relaxed wafer & its
equivalent in SGOI (IBM1) –
expected at 65-nm
• N-channel stress induced by
Si3N4 (Intel2) – introduced at
90-nm
1Rim
et al. “Strained Si CMOS (SS CMOS) technology: oportunities and chalenges”, Solid-State
Electronics 47 (2003) 1133–1139
2Mistry et al. “Delaying forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology”,
2004 Symposium on VLSI Technology, Digest of Technical Papers 50-51
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Thermal Noise in n-Channel s-Si MOSFETs
Si
Si1-xGex
a=1
1+0.042x
Strained Si
(001)
Perpendicular
2 valleys
EC
In-plane
4 valleys
(100)
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(010)
6
4
2
Biaxial tensile strain-induced EC splitting in Si
Thermal Noise in n-Channel s-Si MOSFETs
Typical layer sequence for
a N-channel BC MODFET
N+ Supply layer SiGe
Select Doping level
to adjust VTH
nid Spacer layer Si Ge
nid Strained Si layer
Constant composition Si Ge
Graded Si1-xGex
P+ Si Substrate
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Expensive!!!
Si wafer!!!
Thermal Noise in n-Channel s-Si MOSFETs
Typical layer sequence for
a N-channel BC MOSFET
Si sacrificial layer
SiO2
Supply layer Si0.7 Ge0.3
Supply layer Si0.7 Ge0.3
Si0.7 Ge0.3 Spacer layer
Si0.7 Ge0.3 Spacer layer
Strained Si layer
Strained Si layer
Constant composition Si0.7 Ge0.3
Constant composition Si0.7 Ge0.3
Graded Si1-xGex
Graded Si1-xGex
Si Substrate
Si Substrate
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Thermal Noise in n-Channel s-Si MOSFETs
Strained-Si MOSFETs
vs MODFETs
Trade-off!!!
-More control over the
channel by the gate
-Lower mobilities in the
channel
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Thermal Noise in n-Channel s-Si MOSFETs
Advantages of SC MOSFETs as compared to BC MOSFETs:
•
•
•
•
•
A single epi layer can potentially enhance both electrons and holes mobilities
SC leads to better scaling for nanometric devices
Higher quality of oxides as Ge far from surface
Better channel control (gm potentially higher)
Better S/D resistances (no Ge on the top layer)
Advantages of SC MOSFETs as compared to bulk MOSFETs:
• Extended immunity of Vth face to L reduction
• Enhanced mobility for both electrons and holes
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Thermal Noise in n-Channel s-Si MOSFETs
Vth dependence on Leff
Experimental results from Sugii et al. IEEE Trans. Electron Dev. 49 Dec 2002
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Thermal Noise in n-Channel s-Si MOSFETs
1. SS n-channel FETs
2. Device Under Study & Description of the
simulation
3. DC and RF results
4. Noise Behaviour
5. Conclusions
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Thermal Noise in n-Channel s-Si MOSFETs
Simulated Structures
Description of the transistor:
- SBL composition Si0.7Ge0.3
- VS 0<x<0.3
- QW channel is n.i.d.
- Lg=100nm-20nm
- tox=6nm-2nm
-Assumed Z=1mm
-Implanted S/D regions
-Vds very low
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Gate
n-poly
Source
Strained
Channel
6nm SiO2
8nm QW
500nm
SBL
Virtual Substrate
Drain
Thermal Noise in n-Channel s-Si MOSFETs
Simulation
• 2D Taurus-Medici bipolar simulation
– Parasitic access resistances added RS=RD=100W
– Fermi statistics
– Roldán model to account for mobility degradation at the SiO2/s-Si
interface
– High-field transverse and longitudinal effects on mobility
(Caughey-Thomas model)
– Doping in S/D regions like Si-implanted
•
•
•
•
Hydrodynamic model for electron transport
Parameters from MC simulations
Only thermal noise considered (diffusion noise sources)
No analytic models available, difficulties to use MC codes.
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Thermal Noise in n-Channel s-Si MOSFETs
Noise Calculation
Using the impedance field method (IFM) microscopic AC noise sources distributed
throughout the device are modeled for each dc operating point.
The noise spectral density is calculated as SV(w, i, j) for a couple of electrodes i, j
and using SV(w, i, j) and Yij parameters the current noise spectral density is
calculated SI(w, i, j)1.
1F.
Bonani, G. Ghione, M.R. Pinto, R.K. Smith, “An Efficient Approach to Noise Analysis Through Multidimensional
Phsics-Based Models”, IEEE Transactions on Electron Devices, Vol 45, pp. 261-269, 1998.
Universidad de Salamanca
Thermal Noise in n-Channel s-Si MOSFETs
Presentation Outline
1. Introduction to SS n-channel FETs
2. Device Under Study & Description of the
simulation
3. DC and RF results
4. Noise Behaviour
5. Conclusions
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Thermal Noise in n-Channel s-Si MOSFETs
Transfer Characteristics
Poor Sub-threshold behaviour
SGOI
1e-4
Lgate
1e-5
100nm -0.420 110.0
IDRAIN (A)
1e-6
Vth (V) S(mV/dec)
80nm
-0.429 118.0
60nm
-0.442 131.1
40nm
-0.464 154.0
20nm
-0.502 200.8
1e-7
1e-8
20nm
40nm
60nm
80nm
100nm
1e-9
1e-10
1e-11
-1.0
-0.8
-0.6
-0.4
-0.2
VGATE (volts)
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0.0
0.2
0.4
Significant Vth roll-off
Channel mobility/Subthreshold slope
trade-off (no pockets!!!)
S≈3Soptim
Thermal Noise in n-Channel s-Si MOSFETs
Transconductance
Gate Capacitance
25
1e+0
20
15
Cgg (aF)
Transconductance (S/mm)
20nm
40nm
60nm
80nm
100nm
20nm
40nm
60nm
80nm
100nm
10
1e-1
5
0
-0.2
0.0
0.2
Gate Overdrive (volts)
0.4
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
Gate Overdrive (volts)
Comments: There is a noticeable shift of the maximum of gm
for 20-nm in agreement with the extracted Vth and a large
reduction of Cgs
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0.5
Thermal Noise in n-Channel s-Si MOSFETs
30
-1
Efficiency of the transconductance (volts )
30
25
20nm
40nm
60nm
80nm
100nm
fT (GHz)
20
15
10
5
0
-0.2
0.0
0.2
Gate Overdrive (volts)
0.4
20nm
40nm
60nm
80nm
100nm
25
20
15
10
5
0
-0.2
0.0
0.2
0.4
Gate Overdrive (volts)
Comments:
•At the beginning of the weak-inversion region the cut-off frequency
is larger than 1GHz for Lgate in the studied range.
•Pure gate-length reduction doesn’t guarantees a better behaviour
neither for low-power nor for “conventional” applications.
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Thermal Noise in n-Channel s-Si MOSFETs
Output-Input Capacitive Coupling Feedback: Miller Effect
1e+0
0.65
0.60
0.55
Cgd/Cgg ratio
Cgd (aF)
20nm
40nm
60nm
80nm
100nm
1e-1
20nm
40nm
60nm
80nm
100nm
0.50
0.45
0.40
0.35
-0.2
-0.1
0.0
0.1
0.2
Gate Overdrive (volts)
0.3
0.4
0.5
0.30
-0.2
0.0
0.2
0.4
Gate Overdrive (volts)
Comments:
•In strong accumulation the feedback capacitance saturates at 60%.
•Pure gate-length reduction doesn’t guarantees a better AC behaviour for low-power
applications!
Universidad de Salamanca
Thermal Noise in n-Channel s-Si MOSFETs
Presentation Outline
1. SS n-channel FETs
2. Device Under Study & Description of the
simulation
3. DC and RF results
4. Noise Behaviour
5. Conclusions
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Thermal Noise in n-Channel s-Si MOSFETs
NFmin vs Idrain
10MHz
20nm
40nm
60nm
80nm
100nm
15
10
5
15
10
1e-7
1e-6
1e-5
IDRAIN (A)
10
0
1e-8
1e-7
1e-6
1e-5
IDRAIN (A)
Starting @ 0.1mW
20-nm non optimal in terms of NFmin!!!
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15
5
0
1e-8
20nm
40nm
60nm
80nm
100nm
20
5
0
1GHz
25
20nm
40nm
60nm
80nm
100nm
20
NFmin (dB)
NFmin (dB)
20
100MHz
25
NFmin (dB)
25
1e-8
1e-7
IDRAIN (A)
1e-6
1e-5
Thermal Noise in n-Channel s-Si MOSFETs
Noise figure @ 1GHz Analysis
1.8e+7
0.40
0.30
1.6e+7
20nm
40nm
60nm
80nm
100nm
20nm
40nm
60nm
80nm
100nm
1.4e+7
1.2e+7
Rnoise (W)
0.35

0.25
0.20
1.0e+7
8.0e+6
6.0e+6
4.0e+6
0.15
2.0e+6
0.10
0.0
0.05
1e-8
1e-7
1e-6
IDRAIN (A)
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1e-5
1e-8
1e-7
1e-6
IDRAIN (A)
1e-5
Thermal Noise in n-Channel s-Si MOSFETs
Noise figure @ 1GHz Analysis
SI,GATE @ 1GHz
SI,DRAIN @ 1GHz
1e-20
1e-21
2
1e-18
20nm
40nm
60nm
80nm
100nm
Spectral Density (mA /Hz)
Spectral Density (mA2/Hz)
1e-17
1e-19
20nm
40nm
60nm
80nm
100nm
1e-22
1e-23
1e-24
1e-20
1e-7
1e-6
Gate Overdrive
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1e-5
1e-7
1e-6
Gate Overdrive
1e-5
Thermal Noise in n-Channel s-Si MOSFETs
Evolution of NFmin with frequency (20nm)
18
16
14
1GHz
100MHz
10MHz
NFmin (dB)
12
10
8
6
4
2
0
1e-7
1e-6
1e-5
Idrain (A)
The range of minimum NFmin shrinks as f increases whereas
gm,max stands at VGS>Vth (≈0.5mW)
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Thermal Noise in n-Channel s-Si MOSFETs
Transfer Characteristics
1e-4
IDRAIN (A)
1e-5
tox
Vth (V) S(mV/dec)
2nm
-0.467 148.0
3nm
-0.477 118.0
4nm
-0.487 131.1
5nm
-0.497 154.0
6nm
-0.506 200.8
1e-6
1e-7
2nm
3nm
4nm
5nm
6nm
1e-8
1e-9
-1.0
-0.5
0.0
VGATE (volts)
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0.5
1.0
Moderate impact on S
Thermal Noise in n-Channel s-Si MOSFETs
Lgate=20nm, varying tox
25
2nm
3nm
4nm
5nm
6nm
NFmin (dB)
20
15
10
5
0
-0.2
0.0
0.2
Gate Overdrive (volts)
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0.4
Thermal Noise in n-Channel s-Si MOSFETs
Scaled structures comparison
0.40
0.35
0.30
25
20nm_2nm
40nm_4nm
60nm_6nm
20
20nm_2nm
40nm_4nm
60nm_6nm
15

NFmin
0.25
0.20
10
0.15
5
0.10
0.05
1e-8
1e-7
1e-6
IDRAIN (A)
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1e-5
0
1e-8
1e-7
1e-6
X Data
1e-5
Thermal Noise in n-Channel s-Si MOSFETs
Conclusions
A study of the thermal noise @ 300K in the channel of a s-Si
SCMOSFET has been presented.
No special precautionary measures were taken against SCE to reduce Lgate (scaling)
SCE must be mitigated without degrading the channel mobility (SGOI)
Therefore: high-mobility in the channel has been preserved, but both a roll off of Vth
and a significant S degradation arise for short enough gate lengths
The cut-off frequency at Vth exhibits a maximum, but it moves out of the low-power
region when Lgate decreases in the range 20-100nm.
Gate length shrinking doesn’t guarantees a better NFmin at low currents and leads to
noticeable degradation for positive values of gate overdrive in excess of 0.2V.
Finally we shows that the current level at which optimum NFmin is achieved is stable with f
in the range (1MHz-1GHz) and it is close to the one that provides gm,max.
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Thermal Noise in n-Channel s-Si MOSFETs
This work was partly funded by EPSRC, MCYT and JCyL
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Thermal Noise in n-Channel s-Si MOSFETs
Method for thermal noise calculation (Goo et al. IEEE Trans. Electron Dev. 47 Dec 2000)
Sin 
in2
qnmac yz
yz
 4q 2 nDn
 4kTn
f
x
x
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Thermal Noise in n-Channel s-Si MOSFETs
2
S id  Ad S in
IFM
2
S ig  Ag S in


S ig id  Ag Ad* S in
Ad ( x) 
id
Y21 ( x, L)

in Y22 (0, x)  Y11 ( x, L)
Y21 ( x, L
Ag ( x) 
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ig
in
 1 
Y12 (0, x)  Y21 ( x, L)
Y22 (0, x)  Y11 ( x, L)
Thermal Noise in n-Channel s-Si MOSFETs
Transmission Line Model
A
B
1  jwr0C gd
1  g m r0
r0
1  g m r0
C
D
w 2 r0C gsC gd
1  g m r0


jw C gs  (1  g m r0 )C gd
1  g m r0
1  g m r0  jwr0C gs
1  g m r0
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
 A B   Y11g

  
 C D   Y21g
Y12 g   Y11s
  
Y22 g   Y21s
Y12s 

Y22s 
Thermal Noise in n-Channel s-Si MOSFETs
Out of the threshold region y=8nm (QW)
S in 
i
qNm ac
 4kTelec
f
x 2
2
n
Telec,N
1000
900
VGS = 1.00 V
VGS = 0.85 V
800
ID-VGS @ 50mV
VTH=-233mV
S=72mV/decade
Z=100mm
x=5nm
y=8nm
Temperature (K)
VGS = 0.75 V
VGS = 0.65 V
700
600
500
400
300
200
0.0
0.2
0.4
0.6
Position (mm)
Electron’s temperature @
VGS=1V
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0.8
Thermal Noise in n-Channel s-Si MOSFETs
600
500
Noise across the channel
Electrons
400
300
1e-8
200
Vgs = 1.00 V
Vgs = 0.85 V
Vgs = 0.75 V
Vgs = 0.65 V
VGS = 1.00 V
-1
VGS = 0.75 V
Noise Spectrum (A Hz )
VGS = 0.85 V
100
2
VGS = 0.65 V
0
0.0
0.2
0.4
0.6
Position (mm)
Carrier number profile
0.8
1e-9
0.1
0.2
0.3
0.4
0.5
Position (mm)
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0.6
0.7
0.8
0.9
Thermal Noise in n-Channel s-Si MOSFETs
MOSFET vs. MODFET
2500
strain-Si MOSFET VGS - VTH = 1.00 V
Temperature (K)
2000
Si MOSFET VGS - VTH = 1.00 V
1500
1000
500
0.0
0.2
0.4
0.6
0.8
Position (mm)
Importance of the lateral design to reduce the Tn!!!
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Thermal Noise in n-Channel s-Si MOSFETs
Influence of the bias point
Vgs=0.15V
Vgs=0.25V
Vgs=0.35V
Vgs=0.45V
Vgs=0.55V
Vgs=0.65V
Vgs=0.75V
Vgs=0.85V
Vgs=1.00V
1e-17
0.0
0.2
1400
0.4
Position (microns)
0.6
Electron temperature (K)
Vgs=0.15V
Vgs=0.25V
Vgs=0.35V
Vgs=0.45V
Vgs=0.55V
Vgs=0.65V
Vgs=0.75V
Vgs=0.85V
Vgs=1.00V
1200
1000
0.8
800
600
1e-8
400
200
0.0
0.2
0.4
Position (mm)
Changing VGS
VDS is kept constant
0.6
0.8
Spectral density (A2 s)
Absolute Value of Electron charge (C)
1e-16
1e-9
1e-10
0.0
0.2
0.4
Position (mm)
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0.6
0.8
Thermal Noise in n-Channel s-Si MOSFETs
Influence of the SBL doping @ ND
Gate
1.1016cm-3
1.1017cm-3
1.1018cm-3
ND
Source
5nm SiO2
8nm QW
500nm
SBL
Drain
Current Spectral Density (A 2s)
1e-8
n-poly
1e-9
Virtual Substrate
0.0
0.2
0.4
Position (microns)
VDS & VGS-VTH kept constant
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0.6
0.8
Thermal Noise in n-Channel s-Si MOSFETs
Impact of Lg (VDS scaled down )
1000
Lg_0.3micron
Lg_0.4micron
Lg_0.45micron
800
600
400
200
0.0
0.2
0.4
0.6
Position (mm)
0.8
1.0
Current Spectral Density (A2s)
Electron Temperature (K)
1200
1e-8
Lg_0.3micron
Lg_0.4micron
Lg_0.45micron
1e-9
0.0
0.2
0.4
0.6
Position (mm)
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0.8
1.0
Thermal Noise in n-Channel s-Si MOSFETs
Acknowledgements
This work was partly funded by EPSRC (UK) under grant GR/N65844/01,
Ministerio de Ciencia y Tecnología (Spain) under grant number TIC2001-1757 and
Consejería de Educación, Cultura y Turismo Junta de Castilla y León under grant
SA066/02.
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