Lecture 12
Latches
Section 5.1-5.3
Schedule
3/10
3/12
3/13
3/17
3/19
3/20
3/24
3/26
3/27
Monday
Wednesday
Thursday
Monday
Wednesday
Thursday
Monday
Wednesday
Thursday
Latches (1)
Flip-flops
Flip-flops, D-latch
Spring break
Spring break
Spring break
Analysis of clocked sequential circuit (1)
Analysis of clocked sequential circuit (2)
Clocked sequential circuit
5.1-5.3
5.4
5.5
5.5
Please bring a functional random number generator to class on Thursday
(3/13).
Outline
• A brief overview of sequential circuits
• Memory elements
– NAND based SR latch
– NAND based D latch
• Verilog Modeling
Combinational Circuits
The outputs {𝐶3 , 𝐶2 , 𝐶1 , 𝐶0 } are determined exclusively by the inputs,
i.e., {𝐴0 , 𝐴1 } and {𝐵0 , 𝐵1 } .
Block Diagram of Sequential
Circuit
New output is dependent on the inputs and the
preceding states of the circuit stored in the
memory.
Characteristic: the output node is intentionally
connected back to inputs of combinational
circuits.
Combinational Vs. Sequential
Circuits
Combinational Circuit
Sequential Circuit
Sequential Circuits
• Two types of sequential circuits
– Synchronous: circuits whose behavior can
be defined from its signals at discrete
instants of time. Clocks are to achieve
synchronization.
– Asynchronous circuits depend on input
signals and the order in which the inputs
change. (No clock pulses are used!)
Block Diagram of Sequential
Circuit
Revise
Sychronous circuits:
Used clocked flip-flops
Asychronous circuits:
Use unclocked flip-flops or time
delay elements
Applications of Asynchronous
Circuits
• Asynchronous circuits are important
where the digital system must respond
quickly without having to wait for a
clock pulse
• Useful in small independent circuits
that require only a few components—
where it may not be practical to go to
the expense of providing a circuit for
generating clock pulses!
Asynchronous Sequential Circuit
(Optional Slides)
Y1=xy1+x’y2
Y2=xy’1+x’y2
Maps and Transition Table
(Optional Slides)
stable states: y1y2=Y1Y2
Toggle x (Optional Slides)
X= 0→1 → 0 → 1
Memory Storage Elements
Latches
• Latches are level sensitive.
• Latches propagate values from input
to output continuously.
• Inputs
– Active low inputs are enabled by 0s.
– Active high inputs are enabled by 1s.
S=1 and R=1
1
𝑄
1
𝑄
S=1 and R=1: holds the current state
S=0 and R=0
0
1
1
0
S=0 and R=0: 𝑄 = 𝑄 = 1
The outputs are not complementary.
This is not a state we want to be in.
S=1 and R=0
1
1
0
0
S=1 and R=0: 𝑄 = 0; 𝑄 = 1
The outputs (𝑄and 𝑄)are complementary.
S=0 and R=1
0
0
1
1
S=0 and R=1: 𝑄 = 1; 𝑄 = 0
The outputs (𝑄and 𝑄)are complementary.
Observations
0
1
1
0
0
1
1
0
S=1 and R=0: 𝑄 = 0; 𝑄 = 1
S=0 and R=1: 𝑄 = 1; 𝑄 = 0
Use active low inputs (i.e. logic “0”) to produce changes
at the outputs.
SR Latch with NAND Gates
S must go back to 1 (the hold mode)
R must go back to 1 (the hold mode)
in order to avoid S=R=0.
in order to avoid S=R=0.
Q and Q’ do not change states when S Q and Q’ do not change states when R
goes back to 1.
goes back to 1.
1. Both inputs of the latch remain at 1 unless the state has to be changed.
2. When both S and R are equal to 1, the latch can be in either the set or the
reset, depending on which input was most recently a 1.
Symbol of the NAND based SR
latch
Active low
inputs
SR latch with Control Line (En=0)
1
0
1
1. En=0, Q and Q’ will not be changed!
SR latch with Control Line (En=1)
S’
1
R’
1. En=1, Q and Q’ will be affected by S and R.
2. We now have active-high enabled circuit!
Comparison
D Latch
(An Improvement Over SR
Latch)
D Latch
D Latch (En=0)
1
0
1
(hold mode)
D Latch (En=1)
D’
1
D
Q follows D as long as En is asserted (En=1).
Data is temporary stored when En is disabled.
D-latch Operation
Verilog
Outline
• Continuous Assignment
• Procedural statement
– Blocking statement
– Non-blocking statement
Continuous Statement
The updating of a continuous statement is triggered whenever
there is a change on the right hand side of the equation.
The assign keyword is used is used.
Procedural Statements
• Procedural statements are executed when the
condition is met.
– Usually the condition is implemented with initial
and always statements.
– There are two types of procedural statements:
blocking and non-blocking statements.
– The left-hand side of the procedural statements
must be the reg data type.
Blocking versus Nonblocking
Statements
• There are two kinds of procedural assignments:
– Blocking statements
• Use (=) as the assignment operator
• Blocking statements are executed sequentially in the
order they are listed.
• Used to model behavior that are level sensitive (i.e. in
combinational logic)
– Nonblocking statements
• Use (<=) as the assignment operator
• Non-blocking statements are executed concurrently.
• Used to model synchronous/concurrent behavior.
Blocking Statements
• B=A (transfers A to B)
• C=B+1 (increments B and writes the value to C)
Non-blocking Statements
• B<=A
• C<=B+1
– The value of A is kept in one storage location
– The value of B+1 is stored in another storage
location
– After all the expressions in the block are
evaluated and stored, the assignment to the
targets on the left-hand side is made.
– C will contain the original value of B, plus 1. This is
the value of B before A is written into B.
Example of a Non-blocking
Statements
X,Y, vectornum are updated concurrently.
Verilog Model of a D Latch
Partial Listing of a Verilog Test
Bench
Output