ECE2030
Introduction to Computer Engineering
Lecture 4: CMOS Network
Prof. Hsien-Hsin Sean Lee
School of Electrical and Computer Engineering
Georgia Tech
CMOS Inverter
• Connect the following terminals of a PMOS and an NMOS
– Gates
– Drains
Vdd
Vdd
Vin
PMOS
Vout
NMOS
Ground
2
Vin
Vdd
OFF
Vin
Vout
Vin
ON
Gnd
Vin = HIGH
Vout = LOW (Gnd)
ON
Vout
Vin
OFF
Gnd
Vin = LOW
Vout = HIGH (Vdd)
2
CMOS Voltage Transfer Characteristics
Vdd
Vin
PMOS
Vout
NMOS
Gnd
OFF: V_GateToSource < V_Threshold
LINEAR (or OHMIC): 0< V_DrainToSource < V_GateToSource - V_Threshold
SATURATION: 0 < V_GateToSource - V_Threshold < V_DrainToSource
Note that in the CMOS Inverter  V_GateToSource = V_in
3
3
Pull-Up and Pull-Down Network
• CMOS network consists of a Pull-UP
Network (PUN) and a Pull-Down
Network (PDN)
• PUN consists of a set of PMOS
transistors
• PDN consists of a set of NMOS
transistors
I0
• PUN and PDN implementations are I1
complimentary to each other
– PMOS  NOMS
– Series topology Parallel topology
4
Vdd
PUN
OUPTUT
….
PDN
In-1
Gnd
4
PUN/PDN of a CMOS Inverter
Vdd
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
5
A
B
0
1
1
Z
A
B
0
Z
1
0
A
B
0
1
1
0
B
A
Gnd
CMOS Inverter
5
Gate Symbol of a CMOS Inverter
Vdd
A
B
B
A
B=Ā
Gnd
CMOS Inverter
6
6
PUN/PDN of a NAND Gate
Pull-Up
Network
Pull-Down
Network
A
B
C
0
0
1
0
1
1
1
0
1
1
1
Z
A
B
C
0
0
Z
0
1
Z
1
0
Z
1
1
0
Vdd
B
A
C
A
B
7
7
PUN/PDN of a NAND Gate
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
8
A
B
C
0
0
1
0
1
1
1
0
1
1
1
Z
A
B
C
0
0
Z
0
1
Z
1
0
Z
1
1
0
A
B
C
0
0
1
0
1
1
1
0
1
1
1
0
Vdd
B
A
C
A
B
8
NAND Gate Symbol
Truth Table
A
B
C
0
0
1
0
1
1
1
0
1
1
1
0
Vdd
B
A
C
A
A
C
B
B
C  AB
9
9
PUN/PDN of a NOR Gate
Pull-Up
Network
Pull-Down
Network
10
A
B
C
0
0
1
0
1
Z
1
0
Z
1
1
Z
A
B
C
0
0
Z
0
1
0
1
0
0
1
1
0
Vdd
A
B
C
A
B
10
PUN/PDN of a NOR Gate
Pull-Up
Network
Pull-Down
Network
Combined
CMOS
Network
11
A
B
C
0
0
1
0
1
Z
1
0
Z
1
1
Z
A
B
C
0
0
Z
0
1
0
1
0
0
1
1
0
A
B
C
0
0
1
0
1
0
1
0
0
1
1
0
Vdd
A
B
C
A
B
11
NOR Gate Symbol
Vdd
Truth Table
A
B
C
0
0
1
0
1
0
1
0
0
1
1
0
A
B
C
A
C
A
B
B
C AB
12
12
How about an AND gate
Vdd
B
A
Vdd
C
A
C
B
A
C=AB
B
Gnd
Inverter
NAND
13
13
An OR Gate
Vdd
A
Vdd
B
C
A
C
B
B
A
C  AB
Gnd
Inverter
NOR
14
14
What’s the Function of the following CMOS Network?
Vdd
A
B
Pull-Up
Network
A
B
C
A
A
Pull-Down
Network
B
B
Combined
CMOS
Network
15
A
B
C
0
0
Z
0
1
1
1
0
1
1
1
Z
A
B
C
0
0
0
0
1
Z
1
0
Z
1
1
0
A
B
C
0
0
0
0
1
1
1
0
1
1
1
0
Function = XOR
15
Yet Another XOR CMOS Network
Vdd
A
B
Pull-Up
Network
A
B
C
A
B
16
Pull-Down
Network
A
B
Combined
CMOS
Network
A
B
C
0
0
Z
0
1
1
1
0
1
1
1
Z
A
B
C
0
0
0
0
1
Z
1
0
Z
1
1
0
A
B
C
0
0
0
0
1
1
1
0
1
1
1
0
Function = XOR
16
Exclusive-OR (XOR) Gate
Vdd
Truth Table
A
A
B
C
0
0
0
0
1
1
1
0
1
1
1
0
A
A
B
B
C
C
A
A
B
B
B
C  AB AB  A  B
17
17
How about XNOR Gate
Truth Table
A
A
B
C
0
0
1
0
1
0
1
0
0
1
1
1
How do we draw the
corresponding CMOS network
given a Boolean equation?
C
B
C  AB AB  A  B
18
18
How about XNOR Gate
Vdd
Truth Table
A
B
C
0
0
1
0
1
0
1
0
0
1
1
1
A
A
A
Vdd
B
B
C
A
A
C
B
B
B
Inverter
C  AB AB
19
XOR
19
A Systematic Method (I)
Start from Pull-Up Network
• Each variable in the given Boolean eqn corresponds to
a PMOS transistor in PUN and an NMOS transistor in
PDN
• Draw PUN using PMOS based on the Boolean eqn
– AND operation drawn in series
– OR operation drawn in parallel
• Invert each variable of the Boolean eqn as the gate
input for each PMOS in the PUN
• Draw PDN using NMOS in complementary form
– Parallel (PUN) to series (PDN)
– Series (PUN) to parallel (PDN)
• Label with the same inputs of PUN
• Label the output
20
20
A Systematic Method (II)
Start from Pull-Down Network
• Each variable in the given Boolean eqn corresponds to a PMOS
transistor in PUN and an NMOS transistor in PDN
• Invert the Boolean eqn
• With the Right-Hand Side of the newly inverted equation, Draw
PDN using NMOS
– AND operation drawn in series
– OR operation drawn in parallel
• Label each variable of the Boolean eqn as the gate input for
each NMOS in the PDN
• Draw PUN using PMOS in complementary form
– Parallel (PUN) to series (PDN)
– Series (PUN) to parallel (PDN)
• Label with the same inputs of PUN
• Label the output
21
21
Systematic Approaches
• Note that both methods lead to exactly the same
implementation of a CMOS network
• The reason to invert Output equation in (II) is
because
– Output (F) is conducting to “ground”, i.e. 0, when there is
a path formed by input NMOS transistors
– Inversion will force the desired result from the equation
• Example
– F=Ā·C + B: When (A=0 and C=1) or B=1, F=1. However,
in the PDN (NMOS) of a CMOS network, F=0, i.e. an
inverse result.
– Revisit how a NAND CMOS network is implemented
• Inverting each PMOS input in (I) follow the same
reasoning
22
22
Example 1 (Method I)
In parallel
Vdd
F  AC  B
In series
(1) Draw the Pull-Up Network
23
23
Example 1 (Method I)
Vdd
In parallel
F  AC  B
In series
A
B
C
(2) Assign the complemented input
24
24
Example 1 (Method I)
Vdd
In parallel
F  AC  B
In series
(3) Draw the Pull-Down Network in
the complementary form
25
A
B
C
A
C
25
Example 1 (Method I)
Vdd
In parallel
F  AC  B
In series
(3) Draw the Pull-Down Network in
the complementary form
A
B
C
C
A
B
26
26
Example 1 (Method I)
Vdd
In parallel
F  AC  B
In series
A
B
C
F
Label the output F
C
A
B
27
27
Example 1 (Method I)
Vdd
In parallel
F  AC  B
A
B
C
In series
Truth Table
28
A
B
C
F
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
F
C
A
B
28
Drawing the Schematic using Method II
F  AC  B
F  AC  B
F  ACB
Vdd
A
B
C
F
F  (A  C)  B
C
A
This is exactly the same
CMOS network with the
schematic by Method I
29
B
29
An Alternative for XNOR Gate (Method I)
Vdd
Truth Table
A
B
C
0
0
1
0
1
0
1
0
0
1
1
1
A
A
A
B
B
C
C
A
B
B
C  AB AB
30
A
B
30
Example 3
F  A  D  B  (A  C)
A
C
A
Start from the innermost term
D
B
A
31
D
31
Example 3
F  A  D  B  (A  C)
A
C
A
Start from the innermost term
D
B
A
D
A
C
32
32
Example 3
F  A  D  B  (A  C)
A
C
A
Start from the innermost term
D
B
A
A
D
B
C
33
33
Example 3
Vdd
F  A  D  B  (A  C)
A
C
A
Start from the innermost term
Pull-Up
Network
D
B
F
A
A
D
B
Pull-Down
Network
C
34
34
Example 4
Vdd
F  (E  D)  (A  D  B  (A  C))
E
D
Start from the innermost term
A
C
B
Pull-Up
Network
A
D
F
A
A
D
E
Pull-Down
Network
B
D
C
35
35
Another Example
F  AC  B
36
How ??
36