1 CAD for Physical Design of VLSI Circuits 2 Course Outline by Topics • Circuit Partitioning • Floorplanning • Placement • Global / Detailed Routing • Technology Mapping in FPGA • Interconnect Optimization 3 VLSI Design Cycle System Specification Circuit Design Architectural Design Physical Design Functional Design Fabrication Logic Design Packaging 4 VLSI Design Cycle Netlist System Specification Physical Design Architectural Design Architectural Specification Functional Design Timing & relationship between functional units Logic Design RTL in HDL Layout Circuit Design or Logic Synthesis Fabrication Chips Packaging Packaged and tested chips 5 VLSI Design Cycle System Specification – Specification of the size, speed, power and functionality of the VLSI system. Architectural Design – Decisions on the architecture, e.g., RISC/CISC, # of ALU’s, pipeline structure, cache size, etc. Such decisions can provide an accurate estimation of the system performance, die size, power consumption, etc. 6 VLSI Design Cycle Functional Design – Identify main functional units and their interconnections. No details of implementation. 7 VLSI Design Cycle Logic Design – Design the logic, e.g., boolean expressions, control flow, word width, register allocation, etc. The outcome is called an RTL (Register Transfer Level) description. RTL is expressed in a HDL (Hardware Description Language), e.g., VHDL and Verilog. X = (AB+CD)(E+F) Y= (A(B+C) + Z + D) 8 VLSI Design Cycle Circuit Design – Design the circuit including gates, transistors, interconnections, etc. The outcome is called a netlist. 9 VLSI Design Cycle Physical Design – Convert the netlist into a geometric representation. The outcome is called a layout. 10 VLSI Design Cycle Fabrication – Process includes lithography, polishing, deposition, diffusion, etc. to produce a chip. Packaging – Put together the chips on a PCB (Printed Circuit Board) or an MCM (Multi-Chip Module) 11 Physical Design Cycle Circuit Partitioning Floorplanning & Placement Routing Layout Compaction Extraction and Verification 12 Physical Design Cycle Circuit Partitioning – Partition a large circuit into subcircuits (called blocks). Factors like #blocks, block sizes, interconnection between blocks, etc. are considered. 1 3 2 13 Physical Design Cycle Floorplanning – Set up a plan for a good layout. Place the modules (modules can be IP blocks, functional units, etc.) at an early stage when details like shape, area, I/O pin positions of the modules, …, are not yet fixed. Deadspace 14 Physical Design Cycle Placement – Exact placement of the modules (modules can be gates, standard cells, etc.) when details of the module design are known. The goal is to minimize delay, total area and interconnect cost. Feedthrough v Standard cell type 1 Standard cell type 2 15 Physical Design Cycle Routing – Complete the interconnections between modules. Factors like critical path, clock skew, wire spacing, etc. are considered. Include global routing and detailed routing. Feedthrough v Type 1 standard cel1 Type 2 standard cell 16 Physical Design Cycle Compaction – Compress the layout from all directions to minimize the total chip area. Verification – Check the correctness of the layout. Include DRC (Design Rule Checking), circuit extraction (generate a circuit from the layout to compare with the original netlist), performance verification (extract geometric information to compute resistance, capacitance, delay, etc.) 17 Design Styles • Full-Custom Design • Standard Cell Design • Gate Array Design • Field Programmable Gate Array Design (FPGA) … or mixtures of the above 18 Full-Custom Design • No rigid restrictions on layout. • More compact design. • Longer design time. • Hierarchical: chip clusters units functional units. 19 Full Custom Design 20 Standard Cell Design • Rectangular cells of the same height. • Cell library (has 500 - 1200 cells). • Cells placed in rows and space between rolls are called channels for routing. • Feedthroughs 21 Standard Cell Design 22 Gate Array Design • Each chip is prefabricated with an array of identical gates or cells. • The chip is “customized” by fabricating routing layers on top. 23 An Uncommitted Gate Array 24 A Committed Gate Array 25 Field Programmable Gate Array • Chips are prefabricated with logic blocks and interconnects. • Logic and interconnects can be programmed (erased and re-programmed) by users. No fabrication is needed. • Interconnects are predefined wire segments of fixed lengths with switches in between. 26 Field Programmable Gate Array 27 Trends in VLSI • Transistor • Smaller, faster, use less power • Interconnect • Less resistive, faster, longer (denser design) • Yield • Smaller die size, higher yield 28 Chip Area micron 29 Processor Performance MIPS 1000,000 100,000 100,000 MIPS 10,000 1,000 100 10 1 0.1 Pentium Pro Processor Pentium Processor 80486 Processor 80386 Processor 80286 8086 75 80 85 90 95 00 05 10 15 Source: Intel 30 Transistor Count K 1,000,000 100,000 10,000 1,000 100 10 1 1975 1980 1985 1990 1995 2000 2005 2010 2015 Projection Source: Intel 31 Average Transistor Price 100 $ 10 1 0.1 0.01 0.001 0.0001 0.00001 0.000001 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 Source: Intel 32 Technology Characteristics Year Technology (m) Density (# transistors / cm2) Chip size (cm2) Power (W) # Routing Layers 1999 2001 2003 2006 2009 2012 0.18 0.15 0.13 0.1 0.07 0.05 6.2M 10M 18M 39M 84M 180M 3.40 4.30 5.20 3.85 1250 1500 6-7 7 6.20 7.50 2100 3500 6000 10000 7 7-8 8-9 9 33 Scaling • The process of shrinking the layout in which every dimension is reduced by a factor is called Scaling. • Transistors become smaller, less resistive, faster, conducting more electricity and using less power. • Designs have smaller die sizes, higher yield and increased performance. 34 Can Scaling Continue? • Scaling work well in the past: Year 1989 Technology 0.65 (m) 1992 1995 1997 1999 2001 0.5 0.35 0.25 0.18 0.15 • In order to keep scaling work in the future, many technical problems need to be solved. 35 Can Scaling Continue? • Some characteristics of transistors do not scale uniformly, e.g., leakage current, threshold voltage, etc. • Mismatch in scaling of transistors and interconnects. Interconnect delay has increased from 5-10% of the overall delay to 50-70%. 36 Roadmap • International Technology Roadmap for Semi-conductors (ITRS) • Projection of future technology requirements for the next 15 years. Edition 1st 2nd 3rd 4th 5th 6th Year of Publication 1992 1994 1997 1999 2001 2003 http://public.itrs.net 37 These trends have brought many changes and new challenges to circuit design. 38 Complicated Design Too many transistors and no way to handle them manually. Solutions: • CAD • Hierarchical design • Design re-use 39 Power and Noise Huge power consumption and heat dissipation becomes a problem Noise and cross talk. Solutions: • Better physical design 40 Interconnect Area Too many interconnects Solutions: • More interconnect layers (made possible by ChemicalMechanical Polishing) • CAD tools for 3-D routing 41 Metal Layers 42 Interconnect Delay Interconnect delay becomes a dominating factor in circuit performance Solutions: • Use copper wire • Interconnect optimization in physical design, e.g., wire sizing, buffer insertion, buffer sizing. 43 Interconnect Delay 40 35 Gate delay Interconnect delay 30 25 20 15 10 5 0 0.65 1989 0.5 1992 0.35 1995 0.25 1998 0.18 2001 0.13 2004 0.1 2007 Source: SIA Roadmap 1997