EZ-COURSEWARE
State-of-the-Art Teaching Tools
From AMS
Teaching Tomorrow’s
Technology Today
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New Trends in VLSI Design
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Processor Performance
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Why is Performance Improving?
• Better circuit design
• More memory, cache and register
• More parallelism (wider data bus,
pipelining, etc.)
• Transistors are switching faster!!!!
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Simple Scaling
Full
Parameter
Scaling
Dimensions:
width, length, oxide thickness
Voltages:
supply, threshold
Intrinsic gate delay
Gate Capacitance
Current per device
Power dissipationwww.advancedmsinc.com
per gate
Constant
Voltage
Scaling
1/S
1/S
1/S
1
1/S
1/S
1/S
1/S2
1/S2
1/S
S
S
Technology (mm)
1.5
1.0Area
0.8
Chip
0.35 0.25
Remark:
mm = mircon
Intel 386 DX
Intel 486 DX
Pentium
Pentium Pro &
Pentium II
0.6
1cm2
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Transistor Count vs. Year
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Average Transistor Price vs. Year
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Can Scaling Continue in Future?
Year
1989 1992 1995 1997 1999
Technology
0.65
0.5
0.35
0.25
0.18
• Scaling
works
well
in
the
past
(mm)
• In order to keep scaling to work in the
future, many technical problems need to be
solved.
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The Roadmap
• National Technology Roadmap for
Semiconductors (NTRS)
• Called ITRS (International TRS) since 4th
Edition
Year of Publication
Ed
• Projection1st
of future technology
1992requirements for
the next 15
years.
2nd
1994
3rd
4th
1997
1999
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Roadmap Overview
• Focus Technology Working Groups
–
–
–
–
–
–
–
Design & Test
Process Integration, Devices & Structures
Front End Process
Lithography
Interconnect
Factory Integration
Assembly & Packaging
–
–
–
–
Environment, Safety & Health
Defect Reduction
Metrology
Modeling & Simulation
• Crosscut Technology Working Groups
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Technology Characteristics
Year
1999 2001 2003
Technology
0.18
0.15
0.13
(mm)
Density
6.2M
10M
18M
2
(#trans./cm )
Chip size
3.40 3.85 4.30
(cm2)
Power
90
110 130
(W)
Frequency
1250 1500 2100
(MHz)
# routing
6-7
7
7
layers
2006 2009
0.1
0.07
2012
0.05
39M 84M 180M
5.20
6.20
7.50
160
170
175
3500 6000 10000
7-8
8-9
9
*Data for high-performance microprocessor
*Data from 97 Edition of Roadmap
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Technical Problems
with Future VLSI Technology
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Too much transistors
• Design are too complicated
• No way to do it manually
• Solutions:
– CAD
– Design hierarchically
– Design reuse
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Area, Performance, Power, Noise
• Important to keep area small.
• How to achieve such a good performance?
• Power consumption is huge.
Heat dissipation is also a problem.
• Both Capacitive and Inductive Noises are not
ignorable now.
• Solutions:
– Physical Design is an appropriate stage to handle all
these.
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– Many research needs
to be done.
Interconnect Area
• Too many interconnects.
• Occupy too much area.
• Solution:
– More interconnect layers.
– Made possible by Chemical-Mechanical Polishing
(CMP).
– Note that more layers doesn’t necessarily mean less
interconnect area.
– Also, routing is no longer a 2-D problem.
Hence, new CAD
algorithms needed.
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SEM Photo of Metal Layers
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Cross-Section of Metal Layers
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40
35
Interconnect
Delay
Interconnect Delay
Gate Delay
Delay (ps)
30
25
20
15
10
5
0
0.65
0.5
1989
1992
0.35
1995
0.25
0.18
0.13
0.1
1998
2001
2004
2007
Technology Generation(mm)
Source: SIA Roadmap 97
19
Interconnect Delay
• Dominating factor in determining circuit
performance nowadays.
• Solutions:
– Copper wire
– Low-k (dielectric constant) material
– Interconnect Optimization at physical design
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Design Planning
• Need to plan ahead during the early stages
of VLSI design cycle.
• Need to take physical design into
consideration early.
• Many research needs to be done.
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Summary
• Technology Trend:
–
–
–
–
Transistors are smaller.
Transistors and Interconnects are denser.
Chip areas are larger.
Number of metal layers are more.
• Problems:
–
–
–
–
Design complexity.
Tradeoff of Area, Performance, Power, Noise.
Interconnect area and Interconnect delay.
Increasing planning requirements.
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