‫الگوريتمهاي طراحي فيزيكي ‪VLSI‬‬
‫‪1‬‬
‫مراجع‬
•
•
•
•
•
1.
2.
Andrew B. Kahng, Jens Lienig, Igor L. Markov and Jin Hu, VLSI
Physical Design: From Graph Partitioning to Timing Closure, Springer,
2011.
N. Sherwani, “Algorithms for VLSI Physical Design Automation”, 3rd
edition, Kluwer Academic Publishers, Boston, MA, 1999.
T.H. Cormen, C.E. Leiserson and R.L. Rivest, “Introduction to
Algorithms”, McGraw-Hill, New York, NY, 1990.
Practical Problems in VLSI Physical Design Automation, Sung Kyu Lim,
Springer, 2008.
P. Lee, “Introduction to Place and Route Design in VLSI,” Lulu, 2007.
Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, Handbook of
Algorithms for Physical Design Automation, ed., Taylor & Francis Group,
2009.
L. Scheffer, L. Lavagno, G. Martin, “EDA Handbook (EDA for IC
Implementation, Circuit Design, and Process Technology),”, Ed., CRC
Press, 2006.
2
VLSI CAD Conferences
• DAC
 Design Automation Conference
• ICCAD
 Int’l Conference on Computer-Aided Design
• ISPD
 Int’l Symposium of Physical Design
• ASP-DAC
 Asia and South Pacific DAC
3
VLSI CAD Conferences
• DATE (EDAC)
 Design Automation and Test in Europe
• ISCAS
 Int’l Symposium on Circuits and Systems
• ICCD
 Int’l Conference on Computer Design
• APC-CAS
 Asia-Pacific Conference on Circuits and Systems
4
VLSI CAD Journals
• IEEE TCAD
 IEEE Transactions on CAD
• ACM TODAES
 ACM Transactions on Design Automation of
Electronic Systems
• Integration, the VLSI Journal
• IEEE Transactions on Circuits and
Systems
• IEEE Transactions on VLSI Systems
• IEEE Transactions on Computers
5
Web Sites
•Papers:
http://scholar.google.com/
•Benchmarks:
http://vlsicad.eecs.umich.edu/BK/Slots/slots/Circ
uitandMicroprocessorDesignExamples.html
http://vlsicad.eecs.umich.edu/BK/Slots/slots/Wir
elengthdrivenStandardCellPlacement.html
http://www.cbl.ncsu.edu/benchmarks/
6
Web Sites
• VLSI CAD Bookshelf:
http://vlsicad.eecs.umich.edu/BK/
• VLSI Design Automation Café:
http://www.edacafe.com
7
8
9
10
Integrated Circuits (ICs)
• What are they?
 Electrical components built by layering
different materials on a silicon base (wafer)
• IC Designer
 Transforms a circuit description into a geometric
description - Layout process
11
Integrated Circuits
B
12
Size Issue
50-70 microns
0.020 microns
0.025 microns
Tens of
13
Moore’s Law
In 1965, Gordon Moore:
• Number of transistors on an IC
doubles every year.
• 10 years later, he revised it:
doubles every 18 months
14
VLSI Physical Design Automation
• Modern chip design: very complex
•  Largely performed by specialized
software
Tools are frequently updated to reflect
− improvements in semiconductor technologies
− increasing design complexities
15
VLSI Physical Design Automation
• User of this software needs:
a high-level understanding of the implemented
algorithms.
• Developer of this software needs an
understanding of :
how various algorithms operate and interact
what their performance bottlenecks are
16
Questions
How is functionally correct layout produced
from a netlist? (Analysis)
netlist
physical
design
layout
How do we develop and improve software for
VLSI physical design? (Algorithm design)
17
System
Specification
ENTITY test is
port a: in bit;
end ENTITY test;
Architectural
Design
Functional Design
and Logic Design
Circuit Design
Physical Design
DRC
LVS
Physical Verification
and Signoff
ERC
Fabrication
Packaging
and Testing
Chip
19
System Specification
• Specify overall goals and high-level
requirements:
 Functionality
 Performance
 Physical dimensions
 Production technology
 Overall power constraints
• Trade-offs:
 Market requirements, costs, economical viability
20
Architectural Design
• Define basic architecture to meet the system
specifications:
 Integration of analog and mixed-signal blocks
 Memory management (serial/parallel?) + addressing
scheme
 Number and types of computational cores
− E.g., processors and DSP algorithms/units
 Internal and external communication
− support for standard protocols, …
21
Architectural Design (cont’d)
• Define basic architecture to meet the
system specifications:
 Hard/soft IP blocks
 Pinout, packaging and die-package interface
 Power requirements
 Choice of process technology and layer stacks
22
Functional and Logic Design
• Functional design:
 Main functional units and their
interconnections
 Behavioral specification of each module (not
implementation)
−input-output mapping
−timing behavior
23
Functional and Logic Design
• Logic design:
 RTL spec. in VHDL/Verilog + target library
 Logic synthesis and simulation
  Result: Netlist i.t.o. library elements
24
Netlist
(a: N )
1
(b: N )
2
Pin-Oriented Netlist
(c: N )
5
(x: IN1 N , IN2 N , OUT N )
1
2
3
(y: IN1 N , IN2 N , OUT N )
1
2
4
(z: IN1 N , IN2 N , OUT N )
3
4
5
(N : a, x.IN1, y.IN1)
1
(N : b, x.IN2, y.IN2)
2
(N : x.OUT, z.IN1)
3
(N : y.OUT, z.IN2)
4
(N : z.OUT, c)
5
Net-Oriented Netlist
25
RTL Specification
• RTL:
Control flow
Register allocation
Data path:
−Arithmetic operations
−Logic operations
−Buses and interconnections
26
Circuit Design
• Some critical modules must be designed
at the transistor level:
SRAM blocks
I/O
Analog circuits
High-speed functions
Electro-static discharge (ESD) protection
circuits
• Verification by SPICE simulation
27
Physical Design
Circuit Description
Geometrical Description
Manufacturing
28
System
Specification
ENTITY test is
port a: in bit;
end ENTITY test;
Architectural
Design
Functional Design
and Logic Design
Circuit Design
Physical Design
DRC
LVS
Physical Verification
and Signoff
Partitioning
Chip Planning
Placement
Clock Tree Synthesis
Signal Routing
ERC
Fabrication
Timing Closure
Packaging
and Testing
Chip
29
• DRC:
Physical Verification
 Checks technology-imposed constraints
• Circuit extraction and LVS:
 Layout  netlist
 Compare with original netlist
• Parasitic extraction:
 Layout  RC(L) circuit
 Check for electrical characteristics
• Antenna rule checking:
 Antenna effects damage transistors
• ERC:
 power and ground connections
 signal transition time (slew)
 fan-out constraints
30
Fabrication
• Tapeout (Stream out):
 Generation of layout data in
GDSII format
 Delivering the design to
manufacturing process
• Wafer size: 200-300
mm
• Die size: 25 mm2
− Layout is converted to
several dozens of photolithographic masks
31
Testing and Packaging
32
Physical Design
• Arrange devices on a plane
• Determine interconnection paths so that
Constraints:
− Functionality is preserved
− Performance constraints are met
− Manufacturing design rules are met
Metrics for optimization:
− ….
33
Physical Design
• Metrics:
 Performance:
− Gate delays and interconnect delays
 Area:
−  larger chips  higher costs + slower chips + higher power
 Reliability:
− E.g. vias
 Power consumption
 Yield
• Efficiency of algorithms
34
Physical Design Cycle
Break the circuit up into
Partitioning
Placement/
Floorplanning
Routing
smaller segments
Place the segments on
the chip
Lay out the
wire paths
35
System
Specification
ENTITY test is
port a: in bit;
end ENTITY test;
Architectural
Design
Functional Design
and Logic Design
Circuit Design
Physical Design
DRC
LVS
Physical Verification
and Signoff
Partitioning
Chip Planning
Placement
Clock Tree Synthesis
Signal Routing
ERC
Fabrication
Timing Closure
Packaging
and Testing
Chip
36
)Partitioning( ‫افراز‬
• Reasons:
•
Highly complex circuits
•
Memory limitation of computers
•
Speed limitation of computers
Sets of partitions
Netlist
Number of partitions
Partitioner
Partitions netlist
Block sizes
37
)Partitioning( ‫افراز‬
38
Chip Planning
• Floorplanning:
 Determines shapes and arrangements of modules
 Frequently done manually
• Power & ground routing:
 Distributes VDD and GND nets throughout the chip
• Pin assignment:
 Determines the locations of ports
39
)Floorplanning( ‫جاسازي‬
Recently, SoCs with many cores: Manual
floorplanning not possible
Deadspace
40
)Placement( ‫جايابي‬
41
Clock Network Synthesis
• Determines:
routing of the clock signal
buffering
clock gating (e.g., for power management)
• Constraints to meet
prescribed skew
delay requirements
(power requirement)
42
Clock Network Synthesis
43
)Signal Routing( ‫مسيريابي‬
• Complete interconnections between blocks
 acc. to netlist
• Routing area:
 Channels
 Switchboxes
• Global routing:
 Specifies which channels/switchboxes are to be used
for each net
• Detailed routing:
 Specifies exact interconnections within various ch/sb
44
Global Routing
Cell
1
Cell
2
1
Cell
1
Cell
2
45
Detailed Routing
The actual wires are routed in the channel
The goal of the entire process:
− To produce the shortest wires and consume
the least amount of space
Cell
1
Cell
2
1
Cell
1
Cell
2
46
Timing Closure
• Optimizes circuit performance by specialized
placement and routing techniques
 RC(L) Extraction:
− Layout  circuit
 Timing Analysis:
− Calculate delays and determine critical path(s)
 Timing Optimization
47
History
Time Period
Circuit and Physical Design Process Advancements
1950 -1965
Manual design only.
1965 -1975
Layout editors, e.g., place and route tools, first developed for
printed circuit boards.
1975 -1985
More advanced tools for ICs and PCBs, with more
sophisticated algorithms.
1985 -1990
First performance-driven tools and parallel optimization
algorithms for layout; better understanding of underlying
theory (graph theory, solution complexity, etc.).
1990 -2000
First over-the-cell routing, first 3D and multilayer placement
and routing techniques developed. Automated circuit
synthesis and routability-oriented design become dominant.
Start of parallelizing workloads. Emergence of physical
synthesis.
Design for Manufacturability (DFM), optical proximity
correction (OPC), and other techniques emerge at the designmanufacturing interface. Increased reusability of blocks,
including intellectual property (IP) blocks.
2000 - now
Deeper level of integration (instead of indep’t point tools)
48