ece484ch2

advertisement
Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Manufacturing
Process
July 30, 2002
EE141 Integrated
© Digital
Circuits2nd
1
Manufacturing
CMOS Process
EE141 Integrated
© Digital
Circuits2nd
2
Manufacturing
Photo-Lithographic Process
optical
mask
oxidation
photoresist
removal (ashing)
photoresist coating
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step
EE141 Integrated
© Digital
Circuits2nd
spin, rinse, dry
3
Manufacturing
Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2
Si-substrate
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Hardened resist
SiO
2
(b) After oxidation and deposition
of negative photoresist
Si-substrate
UV-light
Patterned
optical mask
(e) After etching
Exposed resist
Si-substrate
(c) Stepper exposure
EE141 Integrated
© Digital
Circuits2nd
SiO
2
Si-substrate
(f) Final result after removal of resist
4
Manufacturing
CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers
EE141 Integrated
© Digital
Circuits2nd
5
Manufacturing
CMOS Process Walk-Through
p-epi
(a) Base material: p+ substrate
with p-epi layer
p+
SiN
34
p-epi
SiO
2
(b) After deposition of gate-oxide and
sacrificial nitride (acts as a
buffer layer)
p+
p+
EE141 Integrated
© Digital
Circuits2nd
(c) After plasma etch of insulating
trenches using the inverse of
the active area mask
6
Manufacturing
CMOS Process Walk-Through
SiO
2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride
n
p
EE141 Integrated
© Digital
Circuits2nd
(e) After n-well and
V
adjust implants
Tp
(f) After p-well and
V
adjust implants
Tn
7
Manufacturing
CMOS Process Walk-Through
poly(silicon)
(g) After polysilicon deposition
and etch
n+
p+
(h) After n+ source/drain and
p+source/drain implants. These
steps also dope the polysilicon.
SiO
2
(i) After deposition of SiO
insulator and contact hole2etch.
EE141 Integrated
© Digital
Circuits2nd
8
Manufacturing
CMOS Process Walk-Through
Al
(j) After deposition and
patterning of first Al layer.
Al
SiO
2
(k) After deposition of SiO
insulator, etching of via’s, 2
deposition and patterning of
second layer of Al.
EE141 Integrated
© Digital
Circuits2nd
9
Manufacturing
Advanced Metallization
EE141 Integrated
© Digital
Circuits2nd
10
Manufacturing
Design Rules
EE141 Integrated
© Digital
Circuits2nd
11
Manufacturing
3D Perspective
Polysilicon
EE141 Integrated
© Digital
Circuits2nd
Aluminum
12
Manufacturing
Design Rules
Interface between designer and process
engineer
 Guidelines for constructing process masks
 Unit dimension: Minimum line width
 scalable design rules: lambda parameter
 absolute dimensions (micron rules)

EE141 Integrated
© Digital
Circuits2nd
13
Manufacturing
CMOS Process Layers
Layer
Color
Well (p,n)
Yellow
Active Area (n+,p+)
Green
Select (p+,n+)
Green
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact To Poly
Black
Contact To Diffusion
Black
Via
Black
EE141 Integrated
© Digital
Circuits2nd
Representation
14
Manufacturing
Layers in 0.25 mm CMOS process
EE141 Integrated
© Digital
Circuits2nd
15
Manufacturing
Intra-Layer Design Rules
Same Potential
0
or
6
Well
Different Potential
2
9
Polysilicon
2
10
3
Active
Contact
or Via
Hole
3
2
Select
3
Metal1
2
2
3
4
Metal2
3
EE141 Integrated
© Digital
Circuits2nd
16
Manufacturing
Vias and Contacts
2
4
Via
1
1
5
Metal to
1
Active Contact
Metal to
Poly Contact
3
2
2
2
EE141 Integrated
© Digital
Circuits2nd
17
Manufacturing
CMOS Inverter Layout
In
GND
VD D
A
A’
Out
(a) Layout
A
A’
n
p-substrate
n+
p+
Field
Oxide
(b) Cross-Section along A-A’
EE141 Integrated
© Digital
Circuits2nd
18
Manufacturing
Sticks Diagram
V DD
3
Out
In
1
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
“compaction” program
GND
Stick diagram of inverter
EE141 Integrated
© Digital
Circuits2nd
19
Manufacturing
Packaging
EE141 Integrated
© Digital
Circuits2nd
20
Manufacturing
Packaging Requirements
 Electrical:
Low parasitics
 Mechanical: Reliable and robust
 Thermal: Efficient heat removal
 Economical: Cheap
EE141 Integrated
© Digital
Circuits2nd
21
Manufacturing
Bonding Techniques
Wire Bonding
Substrate
Die
Pad
Lead Frame
EE141 Integrated
© Digital
Circuits2nd
22
Manufacturing
Tape-Automated Bonding (TAB)
Sprocket
hole
Film + Pattern
Solder Bump
Die
Test
pads
Lead
frame
Substrate
(b) Die attachment using solder bumps.
Polymer film
(a) Polymer Tape with imprinted
wiring pattern.
EE141 Integrated
© Digital
Circuits2nd
23
Manufacturing
Flip-Chip Bonding
Die
Solder bumps
Interconnect
layers
Substrate
EE141 Integrated
© Digital
Circuits2nd
24
Manufacturing
Package-to-Board Interconnect
(a) Through-Hole Mounting
EE141 Integrated
© Digital
Circuits2nd
(b) Surface Mount
25
Manufacturing
Package Types
EE141 Integrated
© Digital
Circuits2nd
26
Manufacturing
Package Parameters
EE141 Integrated
© Digital
Circuits2nd
27
Manufacturing
Multi-Chip Modules
EE141 Integrated
© Digital
Circuits2nd
28
Manufacturing
Download