Digital Integrated Circuits
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ECE 659 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 EE141 Integrated Circuits2nd © Digital 1 Introduction What is this book all about? Introduction to digital integrated circuits. CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies. What will you learn? Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability EE141 Integrated Circuits2nd © Digital 2 Introduction 1 ECE 659 Digital Integrated Circuits Introduction: Issues in digital design The Th CMOS iinverter t Combinational logic structures Sequential logic gates Design methodologies Interconnect: R, L and C Timing Arithmetic building blocks Memories and array structures EE141 Integrated Circuits2nd © Digital 3 Introduction Introduction Why is designing digital ICs different today than it was before? Will it change in future? EE141 Integrated Circuits2nd © Digital 4 Introduction 2 ECE 659 The First Computer The Babbage Difference Engine (1832) 25,000 parts cost: £17,470 EE141 Integrated Circuits2nd © Digital 5 Introduction ENIAC - The first electronic computer (1946) EE141 Integrated Circuits2nd © Digital 6 Introduction 3 ECE 659 The Transistor Revolution First transistor Bell Labs, 1948 7 Introduction EE141 Integrated Circuits2nd © Digital The First Integrated Circuits Bipolar p logic g 1960’s ECL 3-input Gate Motorola 1966 EE141 Integrated Circuits2nd © Digital 8 Introduction 4 ECE 659 Intel 4004 MicroMicro-Processor 1971 1000 transistors 1 MHz operation EE141 Integrated Circuits2nd © Digital 9 Introduction Intel Pentium (IV) microprocessor EE141 Integrated Circuits2nd © Digital 10 Introduction 5 ECE 659 Moore’s Law zIn 1965 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. zHe made a prediction that semiconductor technology will double its effectiveness ff i every 18 months h 11 Introduction EE141 Integrated Circuits2nd © Digital 1975 1974 1973 1972 1971 1970 1969 1968 1967 1966 1965 1964 1963 1962 1961 1960 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1959 LOG2 OF THE NUMBER OF COMPO ONENTS PER INTEGRATED FUNCTIION Moore’s Law Electronics, April 19, 1965. EE141 Integrated Circuits2nd © Digital 12 Introduction 6 ECE 659 Evolution in Complexity 13 Introduction EE141 Integrated Circuits2nd © Digital Transistor Counts 1 Billion Transistors K 1,000,000 100,000 10,000 1,000 i386 80286 100 10 i486 Pentium® III Pentium® II Pentium® Pro Pentium® 8086 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected EE141 Integrated Circuits2nd © Digital Courtesy, Intel 14 Introduction 7 ECE 659 Moore’s law in Microprocessors Transistors (MT) 1000 2X growth in 1.96 years! 100 10 486 1 P6 Pentium® proc 386 286 0.1 8086 8080 8008 4004 8085 Transistors on Lead Microprocessors double every 2 years 0.01 0.001 1970 1980 1990 Year 2000 2010 15 Introduction Courtesy, Intel EE141 Integrated Circuits2nd © Digital Die Size Growth Die size (mm)) 100 10 8080 8008 4004 1 1970 8086 8085 1980 286 386 P6 486 Pentium ® proc ~7% growth per year ~2X growth in 10 years 1990 Year 2000 2010 Die size grows by 14% to satisfy Moore’s Law EE141 Integrated Circuits2nd © Digital Courtesy, Intel 16 Introduction 8 ECE 659 Frequency Frequency (Mh hz) 10000 Doubles every 2 yyears 1000 100 10 8085 8086 286 386 486 P6 Pentium ® proc 8080 8008 4004 1 01 0.1 1970 1980 1990 Year 2000 2010 Lead Microprocessors frequency doubles every 2 years 17 Introduction Courtesy, Intel EE141 Integrated Circuits2nd © Digital Power Dissipation Power (Watts s) 100 P6 Pentium ® proc 10 8086 286 1 8008 4004 486 386 8085 8080 0.1 1971 1974 1978 1985 1992 2000 Year Lead Microprocessors power continues to increase EE141 Integrated Circuits2nd © Digital Courtesy, Intel 18 Introduction 9 ECE 659 Power will be a major problem 100000 18KW 5KW 1.5KW 500W Power (Wattts) 10000 1000 Pentium® proc 100 286 486 8086 386 8085 8080 8008 1 4004 10 0.1 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive Courtesy, Intel EE141 Integrated Circuits2nd © Digital 19 Introduction Power density Power Density (W W/cm2) 10000 1000 100 Rocket Nozzle Nuclear Reactor 8086 10 4004 Hot Plate P6 8008 8085 Pentium® proc 386 286 486 8080 1 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp EE141 Integrated Circuits2nd © Digital Courtesy, Intel 20 Introduction 10 ECE 659 Not Only Microprocessors Cell Phone Small Signal RF Digital Cellular Market (Phones Shipped) Power RF Power Management 1996 1997 1998 1999 2000 Units Analog Baseband 48M 86M 162M 260M 435M Digital Baseband (DSP + MCU) (data from Texas Instruments) 21 Introduction EE141 Integrated Circuits2nd © Digital Challenges in Digital Design ∝ DSM ∝ 1/DSM “Macroscopic Issues” “Microscopic Problems” • Time-to-Market • Millions of Gates • High-Level Abstractions • Reuse & IP: Portability • Predictability • etc. • Ultra-high speed design • Interconnect • Noise, Crosstalk • Reliability, Manufacturability • Power Dissipation • Clock distribution. distribution Everything Looks a Little Different ? EE141 Integrated Circuits2nd © Digital …and There’s a Lot of Them! 22 Introduction 11 ECE 659 10,000 10,000,000 100,000 100,000,000 Logic Tr./Chip Tr./Staff Month. 1,000 1,000,000 10,000 10,000,000 100 100,000 Productivity Mo. (K) Trans./Staff - M Complexity Logic Transistor pe er Chip (M) Productivity Trends 1,000 1,000,000 58%/Yr. compounded Complexity growth rate 10 10,000 100 100,000 1,0001 10 10,000 x 0.1 100 xx 0.01 10 xx x x 1 1,000 21%/Yr. compound Productivity growth rate x 0.1 100 0.01 10 2009 2007 5 2005 2003 3 2001 1999 1997 1995 5 1993 3 1991 1989 1987 1985 5 1983 3 1981 0.001 1 Source: Sematech Complexity outpaces design productivity EE141 Integrated Circuits2nd © Digital Courtesy, ITRS Roadmap 23 Introduction Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But … How to design chips with more and more functions? Design engineering population does not double every two years… Hence, a need for more efficient design methods Exploit different levels of abstraction EE141 Integrated Circuits2nd © Digital 24 Introduction 12 ECE 659 Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT DEVICE G S n+ EE141 Integrated Circuits2nd © Digital D n+ 25 Introduction Design Metrics How to evaluate performance of a digital circuit (gate, (gate block, block …)? )? Cost Reliability Scalability Speed (delay, operating frequency) P Power dissipation di i ti Energy to perform a function EE141 Integrated Circuits2nd © Digital 26 Introduction 13 ECE 659 Cost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area EE141 Integrated Circuits2nd © Digital 27 Introduction NRE Cost is Increasing EE141 Integrated Circuits2nd © Digital 28 Introduction 14 ECE 659 Die Cost Single die Wafer Going up to 12” (30cm) From http://www.amd.com 29 Introduction EE141 Integrated Circuits2nd © Digital Cost per Transistor cost: ¢-per per--transistor 1 0.1 Fabrication capital cost per transistor (Moore’s law) 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1982 1985 EE141 Integrated Circuits2nd © Digital 1988 1991 1994 1997 2000 2003 2006 2009 2012 30 Introduction 15 ECE 659 Yield No. of good chips per wafer ×100% Total number of chips per wafer Wafer cost Die cost = Dies per wafer × Die yield Y= Dies per wafer = π × (wafer diameter/2)2 π × wafer diameter − die area 2 × die area 31 Introduction EE141 Integrated Circuits2nd © Digital Defects ⎛ defects per unit area × die area ⎞ die yield = ⎜1 + ⎟ α ⎝ ⎠ −α α is approximately 3 die cost = f (die area)4 EE141 Integrated Circuits2nd © Digital 32 Introduction 16 ECE 659 Some Examples (1994) Chip Metal Line layers width Wafer cost Def./ Area Dies/ Yield cm2 mm2 wafer Die cost 386DX 2 0.90 $900 1.0 43 360 71% $4 486 DX2 3 0.80 $1200 1.0 81 181 54% $12 Power PC 601 4 0.80 $1700 1.3 121 115 28% $53 HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73 DEC Alpha 3 0 70 0.70 $1500 12 1.2 234 53 19% $149 Super Sparc 3 0.70 $1700 1.6 256 48 13% $272 Pentium 3 0.80 $1500 1.5 296 40 9% $417 33 Introduction EE141 Integrated Circuits2nd © Digital Reliability― Noise in Digital Integrated Circuits v(t) i(t) Inductive coupling p g EE141 Integrated Circuits2nd © Digital Capacitive p coupling p g V DD Power and g ground noise 34 Introduction 17 ECE 659 DC Operation Voltage Transfer Characteristic V(y) V VOH = f(VOL) VOL = f(VOH) VM = f(VM) f OH V(y)=V(x) VM Switching Threshold V OL V OL V V(x) OH Nominal Voltage Levels 35 Introduction EE141 Integrated Circuits2nd © Digital Mapping between analog and digital signals V “ 1” V OH V IH V out OH Slope = -1 1 Undefined Region V “ 0” V Slope p = -1 IL V OL OL V EE141 Integrated Circuits2nd © Digital IL V IH V in 36 Introduction 18 ECE 659 Definition of Noise Margins "1" V OH V OL NM H NM L V Noise margin high IH V Undefined Region IL Noise margin low "0" Gate Output Gate Input EE141 Integrated Circuits2nd © Digital 37 Introduction Noise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional ti l noise i sources EE141 Integrated Circuits2nd © Digital 38 Introduction 19 ECE 659 Key Reliability Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric – the capability to suppress noise sources Key metrics: Noise transfer functions functions, Output impedance of the driver and input impedance of the receiver; 39 Introduction EE141 Integrated Circuits2nd © Digital Regenerative Property out out v3 v3 f (v) v1 fin v(v) v1 v3 fin v(v) v2 v0 Regenerative EE141 Integrated Circuits2nd © Digital in f (v) v0 v2 in Non-Regenerative 40 Introduction 20 ECE 659 Regenerative Property v0 v1 v2 v3 v4 v5 v6 A chain of inverters V (Volt) 5 v0 3 v1 1 Simulated response 21 0 2 v2 4 6 8 10 t (nsec) 41 Introduction EE141 Integrated Circuits2nd © Digital Fan--in and Fan Fan Fan--out N Fan-out N EE141 Integrated Circuits2nd © Digital M Fan-in M 42 Introduction 21 ECE 659 The Ideal Gate V out Ri = ∞ Ro = 0 Fanout = ∞ NMH = NML = VDD/2 g=∞ V in 43 Introduction EE141 Integrated Circuits2nd © Digital An Old Old--time Inverter 5.0 4.0 NM L 3.0 (V) 2.0 out V VM NM H 10 1.0 0.0 EE141 Integrated Circuits2nd © Digital 1.0 2.0 3.0 V in (V) 4.0 5.0 44 Introduction 22 ECE 659 Delay Definitions V in 50% t tpHL V out tpLH 90% 50% t 10% tf tr 45 Introduction EE141 Integrated Circuits2nd © Digital Ring Oscillator v0 v1 v0 v2 v1 v3 v4 v5 v5 T = 2 × tp × N EE141 Integrated Circuits2nd © Digital 46 Introduction 23 ECE 659 A FirstFirst-Order RC Network R vin vout C tp = ln (2) τ = 0.69 RC Important model – matches delay of inverter 47 Introduction EE141 Integrated Circuits2nd © Digital Power Dissipation Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t) Peak power: Ppeak = Vsupplyipeak Average power: Pave = EE141 Integrated Circuits2nd © Digital Vsupply t +T 1 t +T p ( t ) dt = isupply (t )dt T ∫t T ∫t 48 Introduction 24 ECE 659 Energy and EnergyEnergy-Delay Power-Delay owe De ay Product oduct (PDP) ( D )= E = Energy per operation = Pav × tp Energy-Delay Product (EDP) = quality li metric i off gate = E × tp 49 Introduction EE141 Integrated Circuits2nd © Digital A FirstFirst-Order RC Network R vin E0 vout CL Vdd T T 2 P t dt V i t dt V = = = ( ) ( ) ∫ dd ∫ sup ply l dd ∫ CL dV out = C L • V dd →1 0 0 0 T T Vdd 1 2 E ca p = ∫ P cap ( t ) dt = ∫ V out i ca p( t )dt = ∫ C L Vout dVout = --- C • V dd 2 L 0 0 0 EE141 Integrated Circuits2nd © Digital 50 Introduction 25 ECE 659 Summary Digital integrated circuits have come a long way and still have quite some potential left for th coming the i d decades d Some interesting challenges ahead Getting a clear perspective on the challenges and potential solutions is the purpose of this book Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation EE141 Integrated Circuits2nd © Digital 51 Introduction 26
