Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolić
Timing Issues
January 2003
EE141 Integrated
© Digital
Circuits2nd
1
Timing Issues
Synchronous Timing
CLK
In
R1
EE141 Integrated
© Digital
Circuits2nd
Cin
Combinational
Logic
Cout
R2
Out
2
Timing Issues
Timing
Definitions
EE141 Integrated
© Digital
Circuits2nd
3
Timing Issues
Latch Parameters
D Q
Clk
T
Clk
PWm
D
tsu
thold
tc-q
Q
td-q
Delays can be different for rising and falling data transitions
EE141 Integrated
© Digital
Circuits2nd
4
Timing Issues
Register Parameters
D Q
Clk
T
Clk
thold
D
tsu
tc-q
Q
Delays can be different for rising and falling data transitions
EE141 Integrated
© Digital
Circuits2nd
5
Timing Issues
Clock Uncertainties
4 Power Supply
3 Interconnect
Devices
2
5 Temperature
6 Capacitive Load
7 Coupling to Adjacent Lines
1 Clock Generation
Sources of clock uncertainty
EE141 Integrated
© Digital
Circuits2nd
6
Timing Issues
Clock Nonidealities

Clock skew
 Spatial variation in temporally equivalent clock
edges; deterministic + random, tSK

Clock jitter
 Temporal variations in consecutive edges of the
clock signal; modulation + random noise
 Cycle-to-cycle (short-term) tJS
 Long term tJL

Variation of the pulse width
 Important for level sensitive clocking
EE141 Integrated
© Digital
Circuits2nd
7
Timing Issues
Clock Skew and Jitter
Clk
tSK
Clk
tJS
Both skew and jitter affect the effective cycle time
 Only skew affects the race margin

EE141 Integrated
© Digital
Circuits2nd
8
Timing Issues
Clock Skew
# of registers
Earliest occurrence
of Clk edge
Nominal – /2
Latest occurrence
of Clk edge
Nominal +  /2
Insertion delay
Max Clk skew
Clk delay

EE141 Integrated
© Digital
Circuits2nd
9
Timing Issues
Positive and Negative Skew
In
R1
Combinational
Logic
D Q
CLK
R2
D Q
tCLK1
Combinational
Logic
R3
tCLK2
delay
•••
D Q
tCLK3
delay
(a) Positive skew
In
R1
Combinational
Logic
D Q
tCLK1
R2
D Q
Combinational
Logic
tCLK2
delay
R3
•••
D Q
tCLK3
delay
CLK
(b) Negative skew
EE141 Integrated
© Digital
Circuits2nd
10
Timing Issues
Positive Skew
TCLK + d
CLK1
CLK2
TCLK
1
3
d
2
4
d + th
Launching edge arrives before the receiving edge
EE141 Integrated
© Digital
Circuits2nd
11
Timing Issues
Negative Skew
TCLK + d
1
CLK1
CLK2
2
d
TCLK
3
4
Receiving edge arrives before the launching edge
EE141 Integrated
© Digital
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12
Timing Issues
Timing Constraints
R1
In
D
R2
Q
Combinational
Logic
tCLK1
CLK
tc - q
tc - q, cd
tsu, thold
D
Q
tCLK2
tlogic
tlogic, cd
Minimum cycle time:
T -  = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )
EE141 Integrated
© Digital
Circuits2nd
13
Timing Issues
Timing Constraints
R1
In
D
R2
Q
Combinational
Logic
tCLK1
CLK
tc - q
tc - q, cd
tsu, thold
D
Q
tCLK2
tlogic
tlogic, cd
Hold time constraint:
t(c-q, cd) + t(logic, cd) > thold + 
Worst case is when receiving edge arrives late
Race between data and clock
EE141 Integrated
© Digital
Circuits2nd
14
Timing Issues
Impact of Jitter
TC LK

CLK




t j itter
-tji tte r 
In
CLK
tc-q , tc-q,
ts u, thold
tjitter
EE141 Integrated
© Digital
Combinational
Logic
REGS
Circuits2nd
cd
t log ic
t log ic, cd
15
Timing Issues
Longest Logic Path in
Edge-Triggered Systems
TSU
Clk
TClk-Q
Latest point
of launching
EE141 Integrated
© Digital
Circuits2nd
TJI + 
TLM
T
Earliest arrival
of next cycle
16
Timing Issues
Clock Constraints in
Edge-Triggered Systems
If launching edge is late and receiving edge is early, the data will not be too late if:
Tc-q + TLM + TSU < T – TJI,1 – TJI,2 - 
Minimum cycle time is determined by the maximum delays through the logic
Tc-q + TLM + TSU +  + 2 TJI < T
Skew can be either positive or negative
EE141 Integrated
© Digital
Circuits2nd
17
Timing Issues
Shortest Path
Earliest point
of launching
Clk
TClk-Q TLm
Clk
TH
Nominal
clock edge
EE141 Integrated
© Digital
Circuits2nd
Data must not arrive
before this time
18
Timing Issues
Clock Constraints
in Edge-Triggered Systems
If launching edge is early and receiving edge is late:
Tc-q + TLM – TJI,1 < TH + TJI,2 + 
Minimum logic delay
Tc-q + TLM < TH + 2TJI+ 
EE141 Integrated
© Digital
Circuits2nd
19
Timing Issues
How to counter Clock Skew?


.
REG
REG
In

REG
REG
Negative Skew
log
Out

Positive Skew
Clock Distribution
Data and Clock Routing
EE141 Integrated
© Digital
Circuits2nd
20
Timing Issues
Flip-Flop – Based Timing
Skew

Flip-flop
delay
Logic delay
TSU
TClk-Q
Flip
-flop
=0
=1
Logic
Representation after
M. Horowitz, VLSI Circuits 1996.
EE141 Integrated
© Digital
Circuits2nd
21
Timing Issues
Flip-Flops and Dynamic Logic
Logic delay
TSU
TSU
TClk-Q
TClk-Q
=0
=0
=1
=1
Logic delay
Precharge
Evaluate
Evaluate
Precharge
Flip-flops are used only with static logic
EE141 Integrated
© Digital
Circuits2nd
22
Timing Issues
Latch timing
When data arrives
to transparent latch
tD-Q
D
Q
Latch is a ‘soft’ barrier
Clk
tClk-Q
When data arrives
to closed latch
Data has to be ‘re-launched’
EE141 Integrated
© Digital
Circuits2nd
23
Timing Issues
Single-Phase Clock with Latches

Latch
Logic
Tskl
Tskl
Tskt
Tskt
Clk
PW
P
EE141 Integrated
© Digital
Circuits2nd
24
Timing Issues
Latch-Based Design
L1 latch is
transparent
when  = 0
L2 latch is transparent
when  = 1

L1
Latch
Logic
L2
Latch
Logic
EE141 Integrated
© Digital
Circuits2nd
25
Timing Issues
Slack-borrowing
In
L1
D
Q
CLB_A
t p d,A
a
b
CLK1
L2
D Q
CLB_B
t p d,B
c
L1
d
D
CLK2
Q
e
CLK1
TC LK
CLK1




CLK2
slack passed to next stage
t pd,A
a valid
EE141 Integrated
© Digital
Circuits2nd
tD Q
tpd,B
b valid c valid
t DQ
e valid
d valid
26
Timing Issues
Latch-Based Timing
Skew
Static logic

L1
Latch
Logic
L2 latch
=1
L2
Latch
L1 latch
Logic
Long
path
=0
Can tolerate skew!
Short
path
EE141 Integrated
© Digital
Circuits2nd
27
Timing Issues
Clock Distribution
H-tree
CLK
Clock is distributed in a tree-like fashion
EE141 Integrated
© Digital
Circuits2nd
28
Timing Issues
More realistic H-tree
[Restle98]
EE141 Integrated
© Digital
Circuits2nd
29
Timing Issues
The Grid System
GCL K
Driver
GCLK
Driver
Driver
GCLK
•No rc-matching
•Large power
Driver
GCL K
EE141 Integrated
© Digital
Circuits2nd
30
Timing Issues
Example: DEC Alpha 21164
Clock Frequency: 300 MHz - 9.3 Million Transistors
Total Clock Load: 3.75 nF
Power in Clock Distribution network : 20 W (out of 50)
Uses Two Level Clock Distribution:
• Single 6-stage driver at center of chip
• Secondary buffers drive left and right side
clock grid in Metal3 and Metal4
Total driver size: 58 cm!
EE141 Integrated
© Digital
Circuits2nd
31
Timing Issues
21164 Clocking
tcycle= 3.3ns
trise = 0.35ns

tskew = 150ps
Clock waveform





final drivers


pre-driver
Location of clock
driver on die
EE141 Integrated
© Digital
Circuits2nd
2 phase single wire clock,
distributed globally
2 distributed driver channels


Reduced RC delay/skew
Improved thermal distribution
3.75nF clock load
58 cm final driver width
Local inverters for latching
Conditional clocks in caches to
reduce power
More complex race checking
Device variation
32
Timing Issues
Clock Drivers
EE141 Integrated
© Digital
Circuits2nd
33
Timing Issues
Clock Skew in Alpha Processor
EE141 Integrated
© Digital
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34
Timing Issues
EV6 (Alpha 21264) Clocking
600 MHz – 0.35 micron CMOS
tcycle= 1.67ns
trise = 0.35ns
Global clock waveform

tskew = 50ps
2 Phase, with multiple conditional
buffered clocks
 2.8 nF clock load
 40 cm final driver width




PLL
EE141 Integrated
© Digital
Circuits2nd
Local clocks can be gated “off” to
save power
Reduced load/skew
Reduced thermal issues
Multiple clocks complicate race
checking
35
Timing Issues
21264 Clocking
EE141 Integrated
© Digital
Circuits2nd
36
Timing Issues
EV6 Clock Results
ps
300
305
310
315
320
325
330
335
340
345
ps
5
10
15
20
25
30
35
40
45
50
GCLK Skew
GCLK Rise Times
(at Vdd/2 Crossings)
(20% to 80% Extrapolated to 0% to 100%)
EE141 Integrated
© Digital
Circuits2nd
37
Timing Issues
EV7 Clock Hierarchy
Active Skew Management and Multiple Clock Domains
+ widely dispersed
drivers
DLL
DLL
DLL
NCLK
(Mem Ctrl)
+ DLLs compensate
static and lowfrequency variation
GCLK
(CPU Core)
SYSCLK
EE141 Integrated
© Digital
Circuits2nd
L2R_CLK
(L2 Cache)
PLL
L2L_CLK
(L2 Cache)
+ divides design and
verification effort
- DLL design and
verification is added
work
+ tailored clocks
38
Timing Issues
Self-timed and Asynchronous
Design
Functions of clock in synchronous design
1) Acts as completion signal
2) Ensures the correct ordering of events
Truly asynchronous design
1) Completion is ensured by careful timing analysis
2) Ordering of events is implicit in logic
Self-timed design
1) Completion ensured by completion signal
2) Ordering imposed by handshaking protocol
EE141 Integrated
© Digital
Circuits2nd
39
Timing Issues
Synchronous Pipelined Datapath
In
CLK
R1
D Q
Logic
Block #1
tpd,reg
EE141 Integrated
© Digital
tpd1
Circuits2nd
R2
D Q
Logic
Block #2
tpd2
R3
D Q
Logic
Block #3
R4
D Q
tpd3
40
Timing Issues
Self-Timed Pipelined Datapath
Req
Req
HS
Ack
Done
R1
F1
tpF1
EE141 Integrated
© Digital
HS
Ack
Start
In
Req
Circuits2nd
Start
R2
Req
HS
Ack
Done
F2
tpF2
ACK
Start
R3
Done
F3
Out
tpF3
41
Timing Issues
Completion Signal Generation
LOGIC
In
Out
NETWORK
Start
DELAY MODULE
Done
Using Delay Element (e.g. in memories)
EE141 Integrated
© Digital
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42
Timing Issues
Completion Signal Generation
Using Redundant Signal Encoding
EE141 Integrated
© Digital
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43
Timing Issues
Completion Signal in DCVSL
VDD
VDD
B0
Start
Done
B1
B0
B1
In1
In1
In2
In2
PDN
PDN
Start
EE141 Integrated
© Digital
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44
Timing Issues
Self-Timed Adder
VDD
VDD
Start
C0
C0
P0
C1
G0
P1
C2
G1
P2
C3
G2
P3
Start
C4
C4
G3
Start
VDD
Done
C4
C4
C3
C3
C2
C2
C1
C1
Start
Start
C0
C0
P0
C1
K0
P1
K1
C2
P2
K2
C3
P3
C4
C4
(b) Completion signal
K3
Start
(a) Differential carry generation
EE141 Integrated
© Digital
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45
Timing Issues
Inputs
Start
Input Register
Completion Signal Using Current Sensing
VDD
Start
Output
Static CMOS Logic
A
GNDsense
Current Sensor
tdelay
toverlap
A
B
tMDG
Done
Done
Min Delay Generator
B
Output
EE141 Integrated
© Digital
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tpd-NOR
valid
46
Timing Issues
Hand-Shaking Protocol
Two Phase Handshake
EE141 Integrated
© Digital
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47
Timing Issues
Event Logic – The Muller-C Element
A
F
C
B
(a) Schematic
VDD
A
A
S
B
R
(a) Logic
Q
A
B
Fn+1
0
0
1
1
0
1
0
1
0
Fn
Fn
1
(b) Truth table
VDD
VDD
B
F B
F
B
A
A
F
B
B
(b) Majority Function
(c) Dynamic
EE141 Integrated
© Digital
Circuits2nd
48
Timing Issues
2-Phase Handshake Protocol
Advantage : FAST - minimal # of signaling events (important for global
interconnect)
Disadvantage : edge - sensitive, has state
EE141 Integrated
© Digital
Circuits2nd
49
Timing Issues
Example: Self-timed FIFO
Out
In
R1
En
R2
R3
Done
Reqi
Req0
C
C
C
Acko
Acki
All 1s or 0s -> pipeline empty
Alternating 1s and 0s -> pipeline full
EE141 Integrated
© Digital
Circuits2nd
50
Timing Issues
2-Phase Protocol
EE141 Integrated
© Digital
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51
Timing Issues
Example
From [Horowitz]
EE141 Integrated
© Digital
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52
Timing Issues
Example
EE141 Integrated
© Digital
Circuits2nd
53
Timing Issues
Example
EE141 Integrated
© Digital
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54
Timing Issues
Example
EE141 Integrated
© Digital
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55
Timing Issues
4-Phase Handshake Protocol
Also known as RTZ
Slower, but unambiguous
EE141 Integrated
© Digital
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56
Timing Issues
4-Phase Handshake Protocol
Implementation using Muller-C elements
EE141 Integrated
© Digital
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57
Timing Issues
Self-Resetting Logic
completion
detection
(L1)
Precharged
Logic Block
(L1)
completion
detection
(L2)
Precharged
Logic Block
(L2)
completion
detection
(L3)
Precharged
Logic Block
(L3)
VDD
int
out
A
EE141 Integrated
© Digital
B
Post-charge
logic
C
Circuits2nd
58
Timing Issues
Clock-Delayed Domino
GND
CLK2 (to next stage)
CLK1
VDD
Q1 (also D2)
D1
EE141 Integrated
© Digital
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Pulldown
Network
59
Timing Issues
Asynchronous-Synchronous Interface
fin
Synchronous system
Asynchronous
system
fCLK
Synchronization
EE141 Integrated
© Digital
Circuits2nd
60
Timing Issues
Synchronizers and Arbiters
Arbiter: Circuit to decide which of 2 events
occurred first
 Synchronizer: Arbiter with clock  as one of
the inputs
 Problem: Circuit HAS to make a decision in
limited time - which decision is not important
 Caveat: It is impossible to ensure correct
operation
 But, we can decrease the error probability at
the expense of delay

EE141 Integrated
© Digital
Circuits2nd
61
Timing Issues
A Simple Synchronizer
CLK
int
D
I1
Q
I2
CLK
• Data sampled on rising edge of the clock
• Latch will eventually resolve the signal value,
but ... this might take infinite time!
EE141 Integrated
© Digital
Circuits2nd
62
Timing Issues
Synchronizer: Output Trajectories
Vout
2.0
1.0
0.0
0
100
200
300
time [ps]
Single-pole model for a flip-flop
EE141 Integrated
© Digital
Circuits2nd
63
Timing Issues
Mean Time to Failure
EE141 Integrated
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64
Timing Issues
Example
Tf = 10 nsec = T
Tsignal = 50 nsec
tr = 1 nsec
t = 310 psec
VIH - VIL = 1 V (VDD = 5 V)
N(T) = 3.9 10-9 errors/sec
MTF (T) = 2.6 108 sec = 8.3 years
MTF (0) = 2.5 sec
EE141 Integrated
© Digital
Circuits2nd
65
Timing Issues
Influence of Noise
Uniform distribution
around VM
p(v)
logarithmic
reduction
T
0
VIL
VIH
Initial Distribution
Still Uniform
Low amplitude noise does not influence synchronization behavior
EE141 Integrated
© Digital
Circuits2nd
66
Timing Issues
Typical Synchronizers
2 phase clocking circuit
2
Q
1
Q
2
1
Using delay line
EE141 Integrated
© Digital
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67
Timing Issues
Cascaded Synchronizers Reduce MTF
O1
In
Sync
O2
Sync
Out
Sync
f
EE141 Integrated
© Digital
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68
Timing Issues
Arbiters
Req1
Req2
Ack1
Arbiter
Req1
A
Ack2
B
Ack2
Ack1
(a) Schematic symbol
Req2
Req1
(b) Implementation
Req2
VT gap
A
B
metastable
Ack1
EE141 Integrated
© Digital
Circuits2nd
(c) Timing diagram
t
69
Timing Issues
PLL-Based Synchronization
Chip 1
Chip 2
Data
Digital
System
Digital
System
fsystem = N x fcrystal
Divider
PLL
reference
clock
PLL
Clock
Buffer
fcrystal , 200<Mhz
Crystal
Oscillator
EE141 Integrated
© Digital
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70
Timing Issues
PLL Block Diagram
Reference
clock
Up
Phase
detector
Charge
pump
Loop
filter
VCO
Down
Local
clock
Divide by
N
EE141 Integrated
© Digital
vcont
Circuits2nd
System
Clock
71
Timing Issues
Phase Detector
Output before filtering
Transfer
characteristic
EE141 Integrated
© Digital
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72
Timing Issues
Phase-Frequency Detector
Rst
D Q
B
UP
B
UP = 0
DN = 1
A
A
UP = 0
DN = 0
UP = 1
DN = 0
A
Rst
D Q
DN
A
B
B
(a) schematic
(b) state transition diagram
A
A
B
B
UP
UP
DN
DN
(c) Timing waveforms
EE141 Integrated
© Digital
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73
Timing Issues
PFD Response to Frequency
A
B
UP
DN
EE141 Integrated
© Digital
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74
Timing Issues
PFD Phase Transfer Characteristic
Average (UP-DN)
VDD
-2 p
2p
EE141 Integrated
© Digital
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phase error (deg)
75
Timing Issues
Charge Pump
VDD
UP
To VCO Control Input
DN
EE141 Integrated
© Digital
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76
Timing Issues
PLL Simulation
EE141 Integrated
© Digital
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77
Timing Issues
Clock Generation using DLLs
Delay-Locked Loop (Delay Line Based)
U
fREF
Phase
Det
D
Charge
Pump
DL
Filter
fO
Phase-Locked Loop (VCO-Based)
fREF
U
÷N
PD
D
CP
VCO
Filter
fO
EE141 Integrated
© Digital
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78
Timing Issues
Delay Locked Loop
EE141 Integrated
© Digital
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79
Timing Issues
DLL-Based Clock Distribution
VCDL
•••
Digital
Circuit
•••
Digital
Circuit
CP/LF
Phase
Detector
GLOBAL CLK
VCDL
CP/LF
Phase
Detector
EE141 Integrated
© Digital
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80
Timing Issues