COMBINATIONAL
LOGIC
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
EE415 VLSI Design
Overview
Simple complementary MOS gates
Construction of complex CMOS gates
VLSI cell design methodology
Standard cells
Stick diagrams
Euler path
Delays
Transistor sizing
Fan-in and fan-out considerations
EE415 VLSI Design
Combinational vs. Sequential Logic
In
Combinational
Logic
Circuit
In
Out
Combinational
Logic
Circuit
State
Combinational
Output = f(In)
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Sequential
Output = f(In, Previous In)
Out
Static Complementary CMOS

Pull-up network (PUN) and pull-down network (PDN)
VDD
PMOS transistors only
In1
In2
PUN
InN
In1
In2
InN
pull-up: make a connection from VDD to F
when F(In1,In2,…InN) = 1
F(In1,In2,…InN)
PDN
pull-down: make a connection from F to
GND when F(In1,In2,…InN) = 0
NMOS transistors only
PUN and PDN are dual logic networks
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NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A
B
X
Y
Y = X if A and B
A
X
B
Y
Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
EE415 VLSI Design
PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low
A
B
X
Y
Y = X if A AND B = A + B
A
X
B
Y
Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
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Threshold Drops
VDD
PUN
VDD
S
D
VDD
D
0  VDD
VGS
S
CL
VDD  0
PDN
D
VDD
S
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CL
0  VDD - VTn
CL
VGS
VDD  |VTp|
S
D
CL
Complementary CMOS Logic Style
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Example Gate: NAND
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Example Gate: NOR
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Complex CMOS Gate
B
A
C
D
OUT = D + A • (B + C)
A
D
B
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C
Constructing a Complex Gate
VDD
VDD
C
F
SN4
F
SN1
A
SN3
D
B
C
B
SN2
A
D
A
B
D
C
F
(a) pull-down network
(b) Deriving the pull-up network
hierarchically by identifying
sub-nets
A
D
B
C
(c) complete gate
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Cell Design

Standard Cells
» General purpose logic
» Can be synthesized
» Same height, varying width

Datapath Cells
» For regular, structured designs (arithmetic)
» Includes some wiring in the cell
» Fixed height and width
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Standard Cell Layout
Methodology – 1980s
Routing
channel
VDD
signals
GND
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Standard Cell Layout
Methodology – 1990s
Mirrored Cell
No Routing
channels
VDD
VDD
M2
M3
GND
Mirrored Cell
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GND
Standard Cells
N Well
VDD
Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects
Cell height is “12 pitch”
2
Cell boundary
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In
Out
GND
Rails ~10
Standard Cells
With minimal
diffusion
routing
VDD
VDD
With silicided
diffusion
VDD
M2
In
Out
In
Out
In
M1
GND
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GND
Out
Standard Cells
2-input NAND gate
VDD
VDD
B
A
B
Out
A
GND
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Stick Diagrams
Contains no dimensions
Represents relative positions of transistors
VDD
VDD
Inverter
NAND2
Out
Out
In
GND
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GND
A B
Stick Diagrams
Logic Graph
X
A
PUN
C
j
C
B
i
X
X = C • (A + B)
C
B
VDD
j
i
A
GND
B
A
B
C
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A
PDN
Two Versions of C • (A + B)
A
C
B
A
B
C
VDD
VDD
X
X
GND
GND
uninterrupted diffusion strip
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Consistent Euler Path

An uninterrupted diffusion strip is possible only if there
exists a Euler path in the logic graph

Euler path: a path through all nodes in the graph such that
each edge is visited once and only once.
X
C
i
X
B
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VDD
j
GND
A
A B C
OAI22 Logic Graph
A
C
B
D
X
D
X = (A+B)•(C+D)
C
D
A
B
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C
VDD
X
B
A
B
C
D
PUN
A
GND
PDN
Example: x = ab+cd
x
x
c
b
VDD
x
a
VD D
x
a
d
GND
d
GND
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}
VD D
x
GND
a
b
c
d
(c) stick diagram for ordering {a b c d}
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c
b
Multi-Fingered Transistors
One finger
Two fingers (folded)
Less diffusion capacitance
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CMOS Circuit Styles

Static complementary CMOS - except during switching,
output connected to either VDD or GND via a lowresistance path
» high noise margins
– full rail to rail swing
– VOH and VOL are at VDD and GND, respectively
» low output impedance, high input impedance
» no steady state path between VDD and GND (no static
power consumption)
» delay a function of load capacitance and transistor
resistance
» comparable rise and fall times
EE415 VLSI Design
Switch Delay Model
Req
A
Rp
A
A
Rp
Rp
B
B
Rp
Rn
CL
Rp
A
Cint
A
B
Rn
Rn
Cint
A
A
NAND2
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CL
Rn
Rn
A
B
CL
NOR2
INV
Input Pattern Effects on Delay
Rp
A
Rp
B
Rn


» both inputs go low
CL
– delay is 0.69 Rp/2 CL
B
Rn
A
Delay is dependent on
the pattern of inputs
Low to high transition
» one input goes low
Cint
– delay is 0.69 Rp CL

High to low transition
» both inputs go high
– delay is 0.69 2Rn CL
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Delay Dependence on Input Patterns
3
A=B=10
2.5
Voltage [V]
2
A=1 0, B=1
1.5
A=1, B=10
1
0.5
0
-0.5
0
100
200
time [ps]
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300
400
Input Data
Pattern
Delay
(psec)
A=B=01
67
A=1, B=01
64
A= 01, B=1
61
A=B=10
45
A=1, B=10
80
A= 10, B=1
81
NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF
Transistor Sizing
Rp
2 A
Rp
B
Rn
2
B
2
Rn
A
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Rp
4 B
2
CL
Cint
Rp
4
Cint
A
1
Rn
Rn
A
B
CL
1
Transistor Sizing a Complex
CMOS Gate
A
B
8 6
C
8 6
4 3
D
4 6
OUT = D + A • (B + C)
A
D
1
B
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2
2C
2
Fan-In Considerations
A
B
C
D
A
CL
B
C3
C
C2
D
C1
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Distributed RC model
(Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.
tp as a Function of Fan-In
1250
quadratic
tp (psec)
1000
Gates with a
fan-in
greater than
4 should be
avoided.
750
tpHL
500
250
tp
tpL
linear
H
0
2
4
6
8
fan-in
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10
12
14
16
tp as a Function of Fan-Out
tpNOR2
All gates
have the
same drive
current.
tpNAND2
tp (psec)
tpINV
Slope is a
function of
“driving
strength”
2
4
6
8
10
eff. fan-out
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12
14
16
Problems with Complementary CMOS
•Gate with N inputs requires 2N transistors
•other circuit styles use N+1 transistors
•tp deteriorates with high fan-in
•increases total capacitance
•series connected transistors slow down gate
•fan-out loads down gate
•1 fan-out = 2 gate capacitors (PMOS and NMOS)
t p  a1FI  a2 FI  a3 FO
2
EE415 VLSI Design