NOTICES
•Final Homework 4.10, 4.13, 4.14, 4.18 Due Monday
March 15 Before 12:00 Noon (EECS Mailbox)
•Final Project Report due by Monday March 15
EE415 VLSI Design
NOTICES
•Online Lectures and Quiz Solutions
•Check Grade Page
•Homework
EE415 VLSI Design
NOTICES
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•EE416
•Thank You!
EE415 VLSI Design
Final Exam
•Tuesday March 16 at 8:00 AM in Rm. 317
•Comprehensive (focus on latter part)
•Open Book, Notes, Quizzes, Homework, Lectures
•Open ended questions
•Bring color pencils
•Go though Quizzes and Homework
•Probably 4 questions (may have a choice)
EE415 VLSI Design
SEQUENTIAL LOGIC
Read Chapter 6
EE415 VLSI Design
Master-Slave Flip-Flop


D
A
In
B



Overlapping Clocks Can Cause
• Race Conditions
• Undefined Signals
EE415 VLSI Design

2 phase non-overlapping clocks


D
In



t12
EE415 VLSI Design

2-phase dynamic flip-flop


In
D
Input Sampled


Output Enable
EE415 VLSI Design
Flip-flop insensitive to clock overlap
VDD
VD D
M2

M6
M4
X
In

M3
CL1

M8
D

M1
M7
M5
CL2
Two Modes
•Evaluation
section
section
C2MOS LATCH
EE415 VLSI Design
•Hold
How does C2MOS work?
Operates as a negative edge-triggered master-slave D FF

Two Modes
=1
•Evaluation
In  CL1
=0
CL1  CL2
EE415 VLSI Design
•Hold
Flip-flop insensitive to clock overlap
VDD
VD D
M2

M6
M4
X
In

M3
CL1

M8
D

M1
M7
M5
CL2
Two Modes
•Evaluation
section
section
C2MOS LATCH
EE415 VLSI Design
•Hold
2
C MOS
avoids Race Conditions
condition for signal propagation  active PDN followed by active PUN
VDD
VDD
M2
M6
X
In
1
M3
M1
D
1
M7
M5
(a) (1-1) overlap
only PDN are enabled  input cannot propagate to output
EE415 VLSI Design
2
C MOS
avoids Race Conditions
condition for signal propagation  active PUN followed by active PDN
0
VDD
VDD
M2
M6
M4
X
In
M1
0
M8
D
M5
(b) (0-0) overlap
only PUN are enabled  input cannot propagate to output
EE415 VLSI Design

EE415 VLSI Design

Non-pipelined version
b
REG



.

Pipelined version
log
REG
Out
REG
log
REG
.
REG
b
REG

a
REG
a
REG
Pipelining

Out
Pipelined Logic using
VDD
In
VDD
VDD



F

2
C MOS
C1

C2

NORA CMOS
What are the constraints on F and G?
EE415 VLSI Design
Out
G
C3
Example
VDD
1
VDD
VDD




Number of a static inversions should be even
i.e. logic functions (implemented using static CMOS) between
latches must be non-inverting
EE415 VLSI Design
NORA CMOS
•Stands for NO-RAce CMOS
•Implements fast pipelined datapaths using dynamic logic
•Combines C2MOS pipeline registers and np-CMOS dynamic logic blocks
•Module consists of a comb. logic block (static, dynamic, or mixed)
followed by a C2MOS latch
•Logic and latch are clocked so that both are in evaluation or hold
(precharge) mode simultaneously
•Block which is in evaluation during  = 1 is called a -module
•NORA datapath consists of alternating blocks on  and _BAR modules
EE415 VLSI Design
NORA CMOS Modules
VD D

In1
In2
In3
VDD
VDD

PUN
PDN


Out

(a) -module

Combinational logic
VDD

VDD
Latch
VDD
VD D
In 4

In 1
In 2
In 3
PDN

EE415 VLSI Design
Out

In4
(b)-module
Design Rules for NORA CMOS
The dynamic logic Rule:
•Inputs to a dynamic n (p) block are only allowed to make a 0  1 (1  0)
transition during the evaluation period
The C2MOS Rule:
•The number of static inversions between C2MOS latches should be even
(in the absence of dynamic nodes); if dynamic nodes are present, the
number of static inverters between a latch and a dynamic gate in the logic
block should be even. The number of static inversions between the last
dynamic gate in a logic block and the latch should be even as well.
EE415 VLSI Design
NORA CMOS Modules
VD D

In1
In2
In3
VDD
VDD

PUN
PDN


Out

(a) -module

Combinational logic
VDD

VDD
Latch
VDD
VD D
In 4

In 1
In 2
In 3
PDN

EE415 VLSI Design
Out

In4
(b)-module