Scope and Goals of Future
Design-Through-Mask Integrations
Advanced Reticle Symposium
June 24, 2003
Andrew B. Kahng, UCSD CSE & ECE Departments
email: abk@ucsd.edu
URL: http://vlsicad.ucsd.edu
Andrew Kahng – June 2003
1
Outline
• The Problem, Scope and Goals
• Example 1: Performance-Driven Fill
• Example 2: Cost-Driven RET
• Example 3: Intelligent MDP
• Example 4: Analog Rules, Restricted Layout, …
• Conclusions
Andrew Kahng – June 2003
2
The Problem
• Steadily increasing design effort, turnaround time,
and project risk
• “Dark Future” (12th Japan DA Show talk, 2000)
– Cost and predictability failures 
– Electronics industry makes workarounds
• platforms  programmability  software 
– Semiconductor industry stalls 
– No retooling cycle for supplier industries (e.g., EDA)
Andrew Kahng – June 2003
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Evolutionary Paths
• Conflicting goals
– Designer: “freedom”, “reuse”, “migration”
– EDA: “maintenance mode”
– Process/foundry: “enhance perceived value”
(= add rules)
–  Prisoner’s Dilemma
• Fiddling: Incremental, linear extrapolation of
current trajectory
– “GDS-3”
– Thin post-processing layers (decompaction, RET
insertion, …)
Andrew Kahng – June 2003
4
DAC-2003 Nanometer Futures Panel:
Where should extra R&D $ be spent?
Variability/Litho/Mask/Fab
Power Delivery/Integrity
Low Power/Leakage
Tool/Flow Enhancements/OA
IP Reuse/Abstraction/SysLevel Design
P&R and Opt
DSM Analysis
Others (Lotto)
100%
80%
60%
40%
20%
0%
Intel
IBM
Synopsys
TUEMagma
Cadence
STMicro
Andrew Kahng – June 2003
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Co-Evolutionary Paths
• Designer, EDA, and process communities cooperate
and co-evolve to maintain the cost (value) trajectory of
Moore’s Law
– Must escape Prisoner’s Dilemma
– Must be financially viable
– At 90nm to 65nm transition, this is a matter of survival for the
worldwide semiconductor industry
• Example Focus Areas:
–
–
–
–
–
–
Manufacturability and cost/value optimization
Restricted layout
Intelligent mask data prep
Analog rules
(Layout and design optimizations)
Disclaimer: Not a complete listing
Andrew Kahng – June 2003
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Basic Goals
• Bidirectional design-manufacturing data pipe
– Fundamental drivers: cost, value
• Pass functional intent to mask flow
– Example: RET for predictable circuit performance, function
– RETs should win $$$, reduce performance variation
–  cost-driven, parametric yield constrained RET
• Pass limits of mask flow up to design
– Example: avoid corrections that cannot be manufactured or
verified
N.B.: 1998-2003 papers/tutorials: http://vlsicad.ucsd.edu/~abk/TALKS/
Andrew Kahng – June 2003
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Outline
• The Problem, Scope and Goals
• Example 1: Performance-Driven Fill
• Example 2: Cost-Driven RET
• Example 3: Intelligent MDP
• Example 4: Analog Rules, Restricted Layout, …
• Conclusions
Andrew Kahng – June 2003
8
Layout Density Control
• Area fill: “electrically inactive”, floating or grounded
• Area fill insertion (and slotting)
• Decreases local density variation
•  Decreases post-CMP ILD erosion, conductor dishing
• Cf. “Filling and Slotting: Analysis and Algorithms”, ISPD-98
Features
Post-CMP ILD thickness
Area fill
features
Andrew Kahng – June 2003
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Timing, Parametric Yield Impact
• Performance Impact Limited Fill (PIL-Fill), DAC-2003
• Fill adds capacitance, hurts timing and SI closure
• Plain capacitance minimization objective is not sufficient
• CMP modeling  layout density vs. dimensions built into RLCX
1
Active
lines
top view
2
w
fill grid
pitch
Active
lines
3
A
D
4
buffer distance
F
B
C
E
5
G
6
Andrew Kahng – June 2003
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Min-Slack, Fill-Constrained PIL-Fill
Iterated Greedy Approaches for M SFC PIL-Fill
2500
M i n i m u m S l a c k (ps)
2000
1500
1000
Orig MinSlack
Normal MinSlack
MSFC MinSlack
500
0
1
2
3
4
5
6
-500
-1000
Testcases
• Inputs: LEF/DEF, extracted RSPF, STA (slack) report
• Drive ILP and greedy PIL-Fill methods by estimated lateral
coupling and Elmore delay impact
• Baseline comparison = LP/Monte-Carlo methods
• Iterated greedy method for MSFC PIL-Fill reduces timing slack
impact of fill by 80% (average over all nets), 63% (worst net)
Andrew Kahng – June 2003
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Other Density Management DOF’s
• Splitting for uniformity
Easy connections
through standard via
arrays
– Slotting for uniform CMP
replaced by splitting
– Less data than traditional
slotting
– Power mesh: more
accurate R/C analysis
• Combined density control
and local pattern control
(e.g., fill helps iso-dense,
PSM phase-assignability)
• Details: hierarchy, reuse,
multiple length scales, …
GND
GND
GND
GND
M1
M1
Difficult to connect - where
should vias go?
Illustration courtesy Cadence Design Systems, Inc.
Andrew Kahng – June 2003
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Outline
• The Problem, Scope and Goals
• Example 1: Performance-Driven Fill
• Example 2: Cost-Driven RET
• Example 3: Intelligent MDP
• Example 4: Analog Rules, Restricted Layout, …
• Conclusions
Andrew Kahng – June 2003
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Design for Value*
•
Mask cost trend  Design for Value (DFV)
Design for Value Problem:
Given
•
•
•
•
Performance measure f
Value function v(f)
Selling points fi corresponding to various values of f
Yield function y(f)
Maximize Total Design Value = i y(fi)*v(fi)
[or, Minimize Total Cost]
•
Probabilistic optimization regime
* See "Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer
VLSI", IEEE ASIC/SoC Conference, September 2002, pp. 411-415.
Andrew Kahng – June 2003
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Obvious Step: Function-Aware OPC
• Annotate features with “required amount” of OPC
– E.g., why correct dummy fill?
– Determined by design properties such as setup and hold
timing slacks, parametric yield criticality of devices and
features
• Reduce total OPC inserted (e.g., SRAF usage)
– Decreased physical verification runtime, data volume
– Decreased mask cost resulting from fewer features
• Supported in data formats (OASIS, IBM GL-I)
– Design through mask tools need to make, use annotations
Andrew Kahng – June 2003
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Cost-Driven RET
• MinCorr (DAC-2003): Different levels of RET =
different levels of CD control
Type of
OPC
Aggressive
Medium
No OPC
Ldrawn
(nm)
130
130
130
CD studies due to D. Pramanik, Numerical
Technologies, December 2002
3 of
Ldrawn
5%
6.5%
10%
Figure Delay (, ) for
Count
NAND2X1
5X
(60.7, 7.03)
4X
(60.7, 7.47)
1X
(60.7, 8.79)
OPC solutions due to K. Wampler,
MaskTools, March 2003
Andrew Kahng – June 2003
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MinCorr Results
• Mapping of area minimization to RET cost optimization
• “Yield library” similar to timing libraries (e.g., .lib)
•  Can get an off-the-shelf synthesis tool to perform
OPC “sizing”
• Achieves up to 79% reduction in figure complexity
without any loss of parametric yield
Gate Sizing

MinCorr
Cell Area

Cost of
correction
Nominal
Delay

Delay (+k)
Cycle Time

Selling point
delay
Die Area

Total cost of
OPC
Andrew Kahng – June 2003
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Outline
• The Problem, Scope and Goals
• Example 1: Performance-Driven Fill
• Example 2: Cost-Driven RET
• Example 3: Intelligent MDP
• Example 4: Analog Rules, Restricted Layout, …
• Conclusions
Andrew Kahng – June 2003
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MDP for Minimum NRE
• Mask data prep (MDP)
– Partition layout shapes into multiple gray-scale writing passes
– Determine apertures, beam currents, dwell times, shot ordering, …
– Write error X MEEF gives wafer CD error
• Examples:
– Simplified write of diagonal lines when triangular aperture is available
– Raster vs. Vector write
– Major field layout, subfield scheduling, …
• Driven by performance analyses, sensitivities, costs
• Many other manufacturing NRE optimizations available
Andrew Kahng – June 2003
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Example: Triangular Apertures
www.xinitiative.org
Andrew Kahng – June 2003
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Subfield Scheduling (SPIE Microlithography’03)
• Use of high-energy e-beams in mask writing is limited
by resist heating effects (resist distortion, irreversible
chemical changes)
• Corrective measures (lower beam current density,
delays between flashes, “multi-pass” writing, etc.)
reduce throughput
Mask Writing Schedule Problem
Given: Beam voltage, resist parameters, mask write throughput
requirement
Find: Beam current density and subfield writing schedule to
minimize the maximum resist temperature Tmax
Andrew Kahng – June 2003
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Throughput-Normalized Subfield Scheduling
Max
48.85C
Mean
27.59C
Sequential schedule
Max
37.24C
Mean
20.37C
Lagarias schedule
Max
32.68C
Mean
16.07C
Max
40.49C
Mean
16.97C
Random schedule
Greedy schedule
Andrew Kahng – June 2003
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Outline
• The Problem, Scope and Goals
• Example 1: Performance-Driven Fill
• Example 2: Cost-Driven RET
• Example 3: Intelligent MDP
• Example 4: Analog Rules, Restricted Layout, …
• Conclusions
Andrew Kahng – June 2003
23
Analog Rules
• We don’t need no $#(*&(! “rules”
– Rules just make lithographers feel better (?)
• Ultimately, bottom line is cost of ownership, TCOG
• Given adequate models of MDP, RET and Litho flows,
design tools can and should optimize parametric yield,
$/wafer, profits
– More examples: critical-area reduction by decompaction,
introducing redundancy (vias, wires), …
• Automated learning of models and “implicit rules”
– Current approach: test wafers, test structures, second-hand
understanding
– S. Teig, ISPD-2002 keynote: machine learning techniques
Andrew Kahng – June 2003
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Restricted Layout
• “Soft reset” = 1-time hit on Moore’s Law density scaling
• Restricted Design Rules (“RDR”) can be compensated many ways
– embedded 1-T SRAM fabric, stacking, I/O circuit design, …
– N.B.: Moore’s Law is a “meta” Law!
Dual Exposure Result
Islands
Checkerboard
0
Example:
PhasePhirst!
(Levenson et al.)
180
Transparent
180 Phase Shifters
0
Opaque
Trim Mask Exposure
First Exposure
Dark-Field PSMs
or
M. D. Levenson, 2003
Andrew Kahng – June 2003
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Pre-Made Mask Blanks
• PhasePhirst!
– Levenson/Petersen/Gerold/Mack, BACUS-2000
• Idea: mask blanks can be mass-produced and stored
to reduce average cost (e.g., $10K), then customized
on demand
 0


 0
0
0
M. D. Levenson, 2003
Andrew Kahng – June 2003
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Notes on Regular Layout
• 65 nm has high likelihood for layouts to look like regular gratings
– Uniform pitch and width on metal as well as poly layers
–  Predictable layouts even in presence of focus and dose variations
• More manufacturable cell libraries with regular structures
• New layout challenges (e.g., preserving regularity in placement)
• Caveats
– Non-minimum width poly is less susceptible to variation  larger devices
(with same W/L) may lead to more robust designs (so, selective “upsizing”
may be an alternative to regular layouts)
– 180nm node is a “sweet spot” for cost, analog/mixed-signal integration,
etc.  more and more technology nodes will tend to coexist
Andrew Kahng – June 2003
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Outline
• The Problem, Scope and Goals
• Example 1: Performance-Driven Fill
• Example 2: Cost-Driven RET
• Example 3: Intelligent MDP
• Example 4: Analog Rules, Restricted Layout, …
• Conclusions
Andrew Kahng – June 2003
28
Conclusions
• Designer, EDA, and mask communities must cooperate
and co-evolve to maintain the cost (value) trajectory of
Moore’s Law
– Wakeup call: Intel 157nm announcement
• Basic goal: bidirectional design-mask data pipe
– Drivers: cost, value
– Pass functional intent to mask flow
– Pass limits of mask flow up to design
• Example focus areas (not a complete listing!)
–
–
–
–
–
Manufacturability and cost/value optimization
Restricted layout
Intelligent mask data prep
Analog rules
(Layout and design optimizations)
Andrew Kahng – June 2003
29