Design Technology Issues for
Low-Volume Patterning
SRC/DARPA Workshop
August 9, 2003
Andrew B. Kahng, UCSD CSE & ECE Departments
email: abk@ucsd.edu
URL: http://vlsicad.ucsd.edu
Andrew Kahng – August 2003
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Evolutionary Paths of “DFM”
• Problem: Increasing design effort, turnaround time,
project risk
– Vicious cycle: programmability, structured-ASIC, platform, ESW
• Design, EDA, process communities must co-evolve to
maintain cost (value) trajectory of Moore’s Law
– From 90nm to 45nm, matter of semiconductor industry survival
• Current activity = “fiddling”
– “GDS-3”, thin post-processing layers (decompaction, RET, …)
• Required focus areas (not a complete list):
–
–
–
–
Manufacturability and cost/value optimization
Restricted layout
Intelligent mask data prep
Analog rules
Andrew Kahng – August 2003
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Basic Goal (MLL or otherwise)
• Bidirectional design-manufacturing data pipe
– Fundamentally, driven by cost and value
• Pass functional intent to production flow
– Example: RET for predictable circuit performance, function
– RETs should win $$$, reduce performance variation
–  cost-driven, parametric yield constrained RET
• Pass limits of production flow up to design
– Avoid corrections that cannot be manufactured or verified
• Can Design help? 2x here, 1.5x here  large potential impact
• This talk: sample ideas for synergy with EDA and Design R&D
– (1) Compression; (2) Write; (3) Value (Parametric Yield) and Cost
• Pre-Reading: 2003 Adv. Reticle Symp. talk (= an interesting complement!)
• 1998-2003 papers/tutorials: http://vlsicad.ucsd.edu/~abk/TALKS/
Andrew Kahng – August 2003
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Topic #1: Compression
• Today: RET + complexity  exploding data volume
• Data requirements for direct-write: TB/sec ? (throughput/MAU/…)
• Question #0: How do data volume and delivery gate MLL?
• Question #1: Partitioning of compression and decompression?
– Equipment architecture question – where to put engines, I/F’s, storage?
– Largely orthogonal to design considerations
– Procedural compression largely unexplored? (Ex: Verilog + SP&R binaries
+ runscripts = representation of detail-routed layout)
• Question #2: Design for compressibility?
– What is ROI of relaxing constraints on layout? Of +k bytes of data?
– How context-sensitive must patterning be? (Lessons from RET…)
• Question #3: Use of lossy compression?
– What design features can be “lost”? (Ex: dummy fill)
Andrew Kahng – August 2003
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Compressible Pattern Generation
• Ex: Dummy Fill is added to layout (etch dummy, CMP dummy)
to reduce manufacturing variation, but explodes data volume
• Problem: Compressible Fill Generation. Given a design rulecorrect layout, create a minimum number of regular patterns to
represent area fill features
Andrew Kahng – August 2003
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Design for Compression; Lossy Compression
• “Pixel-domain compression”: Design is a binary (0-1) matrix
11000000
00000111
10100000
10000000
10000001
10000001
00100011
00111101
1: With features
0: Without features
Segment data matrix into blocks
No
Loss allowed?
Yes
Applied one-sided loss to original data matrix
Perform lossless compression on data matrix
 Design for Compression; One-Sided Loss
(DATE ’03, SPIE ML’03)
• Perturbations can improve compressibility
• Asymmetric loss:
• 10 okay! (fill geometry disappears);
• 01 not allowed (fill geometry appears)
END
Andrew Kahng – August 2003
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Restricted Layout ( Compressibility)
• Obvious way of increasing compressibility, with side benefits
• “Soft reset” = 1-time hit on Moore’s Law density scaling
• Restricted Design Rules can be compensated many ways
– embedded 1-T SRAM fabric, stacking, I/O circuit design, …
– Moore’s Law is a “meta” Law!
• 65nm already has high likelihood of grating-like layouts
–
–
–
–
Uniform pitch and width on metal as well as poly layers
Libraries (= template patterns) designed for manufacturability
 Predictable results even in presence of (focus, dose in litho) variations
New layout challenges (e.g., preserving regularity in placement)
• Caveat: non-minimum features less susceptible to variation
– Larger devices (with same W/L) may lead to more robust designs
–  Selective “upsizing” may be alternative to regular minimum layouts
Andrew Kahng – August 2003
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Choice of Geometric Compression Operators
• Who is using compression, at what stages of design-mfg flow?
TYPE 8
• Is there synergy between bzip, etc.
and GDSII-OASIS-UDM? (Not clear
TYPE 7
w.r.t. “decompression efficiency”!)
OASIS Format (recent SEMI standard)
defines eight repetition types.
A repetition represents an “array” of
(polygon) records, enabling compression
of layout data.
TYPE 1
TYPE 2
TYPE 6
TYPE 3
TYPE 4
TYPE 5
equivalent to “GDSII AREF”
Other OASIS repetition types
Andrew Kahng – August 2003
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Topic #2: Writing
• Mask writing: many considerations for technology choice
– Multi-pass grayscale, vector vs. raster, shaped-beam vs. Gaussian spot, …
– Layout density, type of layout, layout data volume, production volume
– Mutually conflicting objectives: resolution, CD control, throughput
• Question #4: Transfer of Mask Write insights to MLL?
– Stripe, major field, subfield boundaries should be defined by design*
– Can write scheduling minimize CD errors due to heating?
N.B.: * Reference: UCSD Technology Transfer Office
Andrew Kahng – August 2003
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Heating and Write Scheduling
• Mask write: resist heating = large contributor to CD
variation
– Lowered using various knobs: Beam current density; Flash
size; Idle times in writing schedule; #passes in MPG
– At cost of reduced write throughput
• Observation: Subfield writing order can be changed to
decrease heating, without decrease in throughput
– Reduced heating  increased beam current density
–  Reduced dwell time compensates for increased travel and
settling time
• MLL: Is heating an issue?
– Explore schedules other than sequential raster
– Are dense layouts more prone to heating errors during write
 constraints on layout density depend on writing schedule?
Andrew Kahng – August 2003
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Write Ordering Changes Thermal Profile
• Two orderings of 16 subfields
1
2
3
4
1
13
5
9
8
7
6
5
6
10
2
14
9
10
11
12
3
15
7
11
16
15
14
13
8
12
4
16
Ordering #1
Ordering #2
• Ordering #2 is “self-avoiding”
• Pre-flash temperature of subfields in Ordering #1 will
be higher than those of subfields in Ordering #2
• Throughput penalty due to “self-avoiding” nature of
Ordering #2 can be offset by increased current density
Andrew Kahng – August 2003
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Ordering in Mask Writing Context
• Significant reductions in temperature of subfields can be obtained
by scheduling writing sequence (SPIE ML ’03, PMJ ’03)
• Simulation of subfield temperatures within a main deflection field
for sequential vs. greedily optimized writing schedules
Max
32.68C
Mean
16.07C
Max
48.85C
Mean
27.59C
Sequential schedule
Greedily optimized schedule
Andrew Kahng – August 2003
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Topic #2: Writing
• Mask writing: many considerations for technology choice
– Multi-pass grayscale, vector vs. raster, shaped-beam vs. Gaussian spot, …
– Layout density, type of layout, layout data volume, production volume
– Mutually conflicting objectives: resolution, CD control, throughput
• Question #4: Transfer of Mask Write insights to MLL?
– Stripe, major field, subfield boundaries should be defined by design*
– Can write scheduling minimize CD errors due to heating?
• Question #5: Anisotropy of write error?
– Ex.: Design awareness of H vs. V error bias due to scan direction?
• Question #6: Compensation of systematic variation?
– Ex.: Deformation of large wafers at clamp or other peripheral locations –
and can this be compensated (instance-wise) in design / direct write?
– Can improve parametric yield and gross die?
Andrew Kahng – August 2003
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Topic #3: Yield and Cost Driven MLL
• Capture designer’s intent: timing, leakage, etc.
– E.g.: “Levels” of accuracy and effort in writing
• Critical poly over active  should be well-controlled
• Higher error tolerance for non-critical poly
• Explicit write time models needed to drive physical
design and library creation
• Question #7: Function-aware write optimizations?
– Shape definitions in data prep (“fracturing”, MPG, etc.)?
– Minimum necessary resolution enhancement?
• Question #8: Layout optimizations?
– Example: iso-dense consideration (~ imaging through focus)
• Question #9: Adaptive write *
– How good is inspection, verification of direct-write?
– If error exists on lower layers, then dummy the layers above
(discard the copy) or reconfigure to work around the error
Andrew Kahng – August 2003
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Design for Value*
Design for Value Problem:
Given
•
•
•
•
Performance measure f
Value function v(f)
Selling points fi corresponding to various values of f
Yield function y(f)
Maximize Total Design Value = i y(fi)*v(fi)
[or, Minimize Total Cost]
Probabilistic optimization regime
* See "Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer
VLSI", IEEE ASIC/SoC Conference, September 2002, pp. 411-415.
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Example: Function-Aware RET
• Potential for large savings in traditional mask flow
• Annotate features with “required amount” of OPC
– E.g., why correct dummy fill?
– Determined by design properties such as setup and hold
timing slacks, parametric yield criticality of devices and
features
• Reduce total OPC inserted (e.g., SRAF usage)
– Decreased physical verification runtime, data volume
– Decreased mask cost resulting from fewer features
• Supported in data formats (OASIS, IBM GL-I)
– Design through mask tools need to make, use annotations
Andrew Kahng – August 2003
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Minimization of Layout Complexity
• MinCorr: Different levels of RET = different
levels of CD control (DAC ’03)
Type of
OPC
Aggressive
Medium
No OPC
Ldrawn
(nm)
130
130
130
CD studies due to D. Pramanik, Numerical
Technologies, December 2002
3 of
Ldrawn
5%
6.5%
10%
Figure Delay (, ) for
Count
NAND2X1
5X
(60.7, 7.03)
4X
(60.7, 7.47)
1X
(60.7, 8.79)
OPC solutions due to K. Wampler,
MaskTools, March 2003
Andrew Kahng – August 2003
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MinCorr Results (OPC, RET)
• Mapping of area minimization to RET cost optimization
• “Yield library” similar to timing libraries (e.g., .lib)
•  Can get an off-the-shelf synthesis tool to perform
OPC “sizing”
• Achieves up to 79% reduction in figure complexity
without any loss of parametric yield
Gate Sizing

MinCorr
Cell Area

Cost of
correction
Nominal
Delay

Delay (+k)
Cycle Time

Selling point
delay
Die Area

Total cost of
OPC
Andrew Kahng – August 2003
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Conclusions
• Design can help: 2x here, 1.5x there, … adds up!
– 10 factors of 2  1024X
• Compression-aware Design
– Orthogonal to equipment architecture
– Design for compressibility ** (** = work at UCSD)
– Lossy (one-sided lossy) layout data compression **
• Writer-aware Design
–
–
–
–
Subfield boundary definition **
Write scheduling to control heating **
Anisotropy of error
Compensation of (wafer-level) systematic variation
• Yield and Cost as direct drivers of Design
– Function-aware write optimizations (criticality, sensitivity, …) **
– Layout optimizations (iso-dense) **
– Adaptive write **
• Many possibilities (+ lots of ideas from Design-Mask-Mfg space)
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