80486 Processor
• 80486 math co-processor is the first processor to have built-in
math coprocessor.
• This being integrated on the chip allows it to execute math
instructions 3 times faster.
• It has 8kb code data internal cache.
• It has five stage instructions pipeline scheme that allows it to
execute instructions much faster than 386.
• It is 168 pin chip.
Signals of 80486
• Address Bus : A31- A2 These are the address lines of the
microprocessor, and are used for selecting memory I/O devices.
However, for memory/IO addressing we also need another set of
signals known as byte enable signals BE0 – BE3. These active-low
byte enable signals (BE0# - BE3#) indicate which byte of the 32-bit
data bus is active during the read or write cycle.
• Data Bus : D0-D31 This is bi-directional data bus with D0 as the
least and D31 as the most significant data bit.
• Data Parity Group: The pins of this group of signals are extremely
important, because they are used to detect the parity during the
memory read and write operations.
• DP0-Dp3: These four data parity input/output pins are used for
representing the individual parity of 4bytes (32bits) of the data
bus.
• Pchk#:the 486 checks the parities of the data bytes read and
signals on the DP0-DP3, if error is found, 486 asserts the Pchk
signal.
• Bus cycle signals
• M/IO#: This output pin differentiates between memory and
I/O operations.
• D/C#: This output pin differentiates between data/control
operations.
• W/R#: This output pin differentiates between read and write
bus cycle.
• PLOCK#: This pseudo lock pin indicates that the current
operation may require more than one bus cycle for its
completion. The bus is to be locked until then.
• LOCK# : This output pin indicates that the current bus cycle is
locked.
• Bus control signals
• ADS# : The address status output pin indicates that a valid bus cycle
definition and addresses are currently available on the corresponding
pins.
• RDY# : This input pin acts as a ready signal for the current non-burst
cycle.
• Bus Arbitration signals
• BREQ : This active high output indicates that the 80486 has generated a
bus request.
• HOLD : This pin acts a local bus hold input, to be activated by another
bus master like DMA controller, to enable to gain the control of the
system bus.
• HLDA : This is an output that acknowledges the receipt of a valid HOLD
request.
• BOFF#: When a CPU requests the access of the bus, and if the bus is
granted to it, then the current bus master which is currently in charge of
the bus will be asked to back off or release the bus.
• Burst Control signals
• These signals are BRDY#, BLAST# are used to control burst
mode memory reads and writes. To start the burst mode 486
sends out the first address and asserts the BLAST# signals.
When the DRAM controller has the first data it asserts BRDY#
signal. Since successive data has to be read, only lower
address bits has to be changed.
• Bus Size Control
• BS8# and BS16# : The bus size-8 and bus size-16 inputs are
used for the dynamic bus sizing feature of 80486. These two
pins enable 80486 to be interfaced with 8-bit or 16-bit devices
though the CPU has a bus width of 32-bits.
• Interrupt Signals:
• RESET : This input pin reset the processor, if its goes high
• INTR : This is a maskable interrupt input that is controlled by
the IF in the flag register
• NMI : This is a non-maskable interrupt input, of type 2.
• Cache Invalidation signals
• AHOLD: The address holds request input pin enables other
bus masters to use the 80486 system bus during a cache
invalidation cycle.
• EADS#: The external address input signal indicates that a valid
address for external bus cycle is available on the address bus.
• Cache Control signals
• KEN# : The cache enable input pin is used to determine
whether the current cycle is cacheable or not.
• FLUSH#: The cache flush input, if activated, clears the cache
contents and validity bits.
• Page caching control
• PCD, PWT : The page cache disables and page write-through
output pins reflect the status of the corresponding bits in
page table or page directory entry.
• Numeric Error Reporting
• FERR : The FERR output pin is activated if the floating point
unit reports any error.
• IGNNE: If ignore numeric processor extension input pin is
activated, the 80486 ignores the numeric processor errors and
continues with processing of data.
What was new?
• Two integer pipeline units are provided so that
two instructions can be handled in parallel in
the pipelines, providing superscalar
performance, that is capability to complete
more than one instruction in one clock cycle.
• Internal data paths of 128 and 256 bits are
used to handle multiple data items of 32 bit
size simultaneously for processing.
Pentium processor
• 486 has 5-stage pipeline
1. Fetch
2. Decode1
3. decode2
4. Data fetch from, or store to, the memory. (ALU)
5. Write the result, back to the destination register
• In Pentium, there are two pipelines provided for
integer operation, after the decode stage.
• Floating point has 8-stage pipeline
Two-integer Pipelines
F
D1
Fetch Instruction
Decode
Instruction
F- instruction Fetch Stage
D1-Decode Stage 1
D2-Decode Stage 2
E-Exucute memory or ALU
WB-Write back to
destination
D2
Generate
Memory Addr
Generate
Memory Addr
D2
E
Do Memory or
ALU Operation
Generate
Memory Addr
E
Write result to
register
Write result to
register
W
B
U-
V-Pipe
W
B
Branch Handling
• Static Predictions – based on instructions.
• Conditional Branch, branch address above the
contents of EIP, it is not taken ; backward jump
is taken.
• Loop – is always taken since the no of times
the branch will be executed is high i.e. except
for the last iteration.
The 4MB page and Flat memory
• The pentium supports the segmented paged model. But the
size of the each page is 4mb rather than 4kb as in 386.
• In large programs, with systems having large physical memory,
it becomes more efficient from operational point of view to
have large pages, so that page swap overhead is reduced.
• Also it shrinks the page management tables.
• In flat memory model we specify the base address of all
segments as 0. so that memory looks like one segment of size
4gb.
Advanced Programmable Interrupt
Controller(APIC)
• Advanced programmable interrupt is in the processor chip in
contrast to 8086 which has priority interrupt controller
external to processor.
• They can be programmed to respond to any I/O interrupts or
even to external interrupt signals from 8259A
• In multiprocessor systems, they can communicate with other
processors and perform inter-processor interrupt
communications.
Multimedia Extension Technology
This technology requires a large amount of data processing.
Example of such processing is image processing, where several
pixels need to be processed to produce the result.
For such type of processing we have to use the concept of
SIMD(single instruction, multiple data) and this concept was first
introduced in Pentium processor.
• We have several MMX(Multimedia Extension) registers for
this purpose. Sometimes floating point registers are also used
for this process.
• The length of MMX data in pentium is 64-bits.
Model Specific Registers(MSRs) and Machine
check(MC) exception
• In pentium processors the special registers were introduced
called as MSR’s to indicate any h/w operation errors.
• The error types are indicated in these registers and recovery
can be guided by these indications which provides a way for
system management.
• The example of these errors can be
• When the bus memory or I/O operation cannot be completed
• During reset some of the h/w routines cannot be loaded.
• When a resource is held indefinitely by some agent , other
devices are waiting for that , some kind of dead lock occurs.
The INIT pin and Built-in-Self Test(BIST)
• At the time of power-on this pin is made 1 and reset pin is
made 0. the 1 on INIT pin will make the BIST program to
execute and check the large part of the processor at least
70%(circuits). The test result will be eax register. If its contents
are 0 it indicates circuit are perfect and the processor is ready
for operation.
• If any other value in eax register , it indicates that processor
circuit is damaged.
• Result in EAX reg : 0 -> no errors.
Any other value -> processor faulty.
System Management Mode(SMM)
• Pentium provides a system management mode,
intended for high-level functions such as power
management and security
• This mode is entered into when an interrupt is
generated at a special pin in the pentium processor,
• Executes CS:EIP; CS=3000H, EIP=8000H.
• All register conditions stored in SMM dump record
prior to entry and the restored when returning to
interrupted environment. It can create sleep mode
and other power saving modes.