EE314
Microprocessor Systems
Chapter 10
Hardware Details on the 8088
Objectives:
The general specification on the 8088 microprocessors
The processor’s control signal names and specifications
General signal relationship and timings
Methods by which the 8088 can interface with external devices
The external interrupt signals and their operations
The 8088 bus controller
The method used to access an 8085 peripheral
Based on "An Introduction to the Intel Family of Microprocessors" by James L. Antonakos
10.3 CPU pin descriptions
0V=“0”,
reference
for all
voltages
Address Bus
(outputs)
Time-multiplexed
Address (outputs)/
Data Bus
(bidirectional)
Hardware
interrupt requests
(inputs)
2...5MHz,
1/3 duty cycle
(input)
Minmode operation
signals (MN/MX=1)
TimeGND 1
40 Vcc
multiplexed
5V±10%
A14
A15
Address Bus
A13
A16/S3
/Status signals
Maxmode
operation
A12
A17/S4
(outputs)
signals (MN/MX=0)
A11
A18/S5
A10
A19/S6
___
A9
SS0 ___ (HIGH)
Control Operation Mode,
A8
MN/MX
Bus
___
(input):
AD7
RD
(in,out)
___ ____
1 = minmode
AD6
8088
HOLD (RQ/GT0)
___ ____
(8088 generates all
AD5
HLDA
(RQ/GT1)
___
______
the needed control
AD4
WR__ (LOCK)
__
signals for a small
AD3
IO/M
(S2)
__
__
Status
system),
AD2
DT/R
(S1)
____
__
signals
AD1
DEN
(S0)
(outputs)
0 = maxmode
AD0
ALE
(QS0)
_____
(8288 Bus
NMI
INTA
(QS1)
_____
Controller expands
INTR
TEST
Interrupt
the status signals to
CLK
READY
acknowledge
generate more
GND 20
21 RESET
(output)
control signals)
10.3 CPU pin descriptions
8088 Status Signals
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Indicated Operation
Interrupt acknowledge
I/O read
I/O write
Halt
Code access
Memory read
Memory write
Passive
Comparison of NMI and INTR
Disabled
via
Interrupt Triggered on: Software Priority
NMI
Rising edge
No
High
INT
High level
Yes
Low
RD
MEMRD
WR
MEMWR
8088 Signal Summary
Signal
CLK
MN/MX
S0,S1,S2
RESET
READY
HOLD
HLDA
NMI
INTR
INTA
RQ/GT0
RQ/GT1
LOCK
ALE
DEN
DT/R
WR
RD
IO/M
AD0-AD7
A8-A19
Input
*
*
Output
*
Tri-State
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Minmode Maxmode
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
IORD
IO/M
IOWR
Decoding 8088 memory and I/O read/write signals
10.4 The 8284 Clock Generator
5V
READY1
READY2
RDY1
RDY2
EFI
CLK
0 = crystal oscillator
F/C
1 = TTL clock on EFI,
CSYNC
synchronized on CSYNC
AEN1
AEN2
8284
4K7
qualifiers for
5V
ASYNC
2X510
READY1,-2
X1
READY
X2 RES RESET
1 = one WAIT state
10MHz
100K
forced by READY
10F
5V
1N4148
1/3 f
osc
1/3 duty cycle
RES
[V]
CLK
X1,2
[V]
t
RESET
1L
0L
t
t
CLK
8088
READY
RESET
0 = forces the P
to froze the
current bus cycle
inserting WAIT
STATES (all
signals keep their
values), allowing
slower devices
time to properly
answer.
A8-A15
74LS244
G1 G2
8282
AD0-AD7
D Q
LE
STB OE
8088
8286
10.5 The 8288 Bus Controller
CPU Address Bus
(A16-A19,
if needed,
should be
latched the
same way like
AD0-AD7)
Data to be transferred
in the current bus cycle
Identify the Memory Byte
(one of 220 (216 in example))
OR the I/O port (one of 216)
to be read OR write
in the current bus cycle
Advanced Write Commands,
providing additional access time
for the selected circuit
Max one active at a time,
identifying Memory vs. I/O
Data
Transmit/Receive
T
and Read vs. Write
Memory ReaD Command
DEN DT/R MRDC
Memory WriTe Command
ALE
MWTC
Input/Output Read Command
S0
IORC
Input/Output Write Command
S1
8288 IOWC
INTerrupt Acknowledge
S2
INTA
Advanced Memory Write Command
AMWC
Advanced Input/Output Write Command
AIOWC
5V
IOB AEN
CEN
Command Enable Control
CPU Data Bus
OE
S0
S1
S2
Status Signals
(codify the bus
cycle type)
Address
Latch
Enable
Data Enable
CLK
I/O Bus only
Address Enable
Bus
10.6 System Time Diagrams - CPU Bus Cycle
CLK
T1
T2
T3
TW
T4
ALE
Address latches store the actual values
IO/M
Memory Cycle (I/O cycle is similar but IO/M = 1)
A16- A19
A16-A19
A8- A15
S3- S6
A8- A15
READY
The slow device drives READY= 0
Read Cycle
(instruction fetch and memory operand read)
RD
AD0- AD7
the P samples READY
(if 0 a WAIT state follows)
A0- A7
DT/R
Tri-state
P reads Data Bus
D0- D7 (Data in)
Direction “READ” for the Data Buffer
Enables Data Buffer
DEN
Memory reads Data Bus
WR
AD0- AD7
DT/R
DEN
Write Cycle (memory operand write)
A0- A7
D0- D7 (Data out)
Direction “READ” for the Data Buffer
Enables Data Buffer
10.6 System Time Diagrams - INT and HOLD
Maxmode Interrupt acknowledge timing
CLK
T1
T2
T3
T4
T1
T2
T3
T4
Prevents P to enter a HOLD state
LOCK
INTA
AD0- AD7
INT type
Tri-state
Second INTA cycle
First INTA cycle
Minmode Interrupt acknowledge timing
CLK
T1
T2
T3
T4
a single INTA cycle in minmode.
INTA
AD0- AD7
two INTA cycles in maxmode, the device
requesting INT has to drive the “INT type”
on the Data Bus, during the second cycle.
Tri-state
INT type
only after ending the current bus cycle
CLK
HOLD
HOLD state: the P releases the Address, HLDA
Data, Control and Status buses (these pins
are tri-sated (high impedance)
HOLD/HLDA Timing
T4
T1
10.7 Personal Computer Bus Standards
Medium Complexity PC Architecture
CPU
Simple P System
Architecture
Cash
Memory
P Bus
Memory
Controller
I/O Bus
Controller
I/O Bus
Memory Bus
Main
Memory
CPU
Memory
P Bus
I/O
PCI (Peripheral Component Interconnect bus)
based Architecture
CPU
Cash
Memory
P Bus
Bridge
Controller
Memory
Controller
Motherboard
I/O Circuits
Memory Bus
PCI (Mezzanine) Bus
I/O Bus
Controller
Main
Memory
Plug-in I/O
Boards
- ISA = Industry Standard
Architecture (8 data bits =
PC-XT bus, or 16 data bits
= PC-AT bus)
- EISA = Extended ISA
- MCA = Micro Channel
Architecture (only IBM)
Motherboard- and Fast
Plug-in I/O Circuits
I/O Bus
Slow Plug-in
I/O Boards
GND
RESETDRV
+5V
IRQ2(9)
-5V
DRQ2
-12V
0WS
+12V
GND
-SMEMW
-SMEMR
-IOW
-IOR
-DACK3
DRQ3
-DACK1
DRQ1
-REFRESH
SYSCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
-DACK2
TC
BALE
+5V
OSC
GND
B1
A1
B5
A5
B10
A10
B15
A15
B20
A20
B25
A25
B30
B31
A30
A31
I/O CH CK
10.7 Personal Computer
SD7
SD6
Bus Standards - ISA Bus
SD5
SD4
-MEMCS16
SBHE
D1
C1
SD3
-IOCS16
LA23
SD2
IRQ10
LA22
SD1
IRQ11
LA21
SD0
IRQ12
LA20
D5
C5
I/O CH RDY
IRQ15
LA19
AEN
IRQ14
LA18
SA19
-DACK0
LA17
SA18
DRQ0
-MEMR
SA17
-DACK5
-MEMW
D10
C10
SA16
DRQ5
SD8
SA15
-DACK6
SD9
SA14
DRQ6
SD10
SA13
-DACK7
SD11
SA12
DRQ7
SD12
D15
C15
SA11
+5V
SD13
SA10
-MASTER
SD14
SA9
GND
SD15
D18
C18
SA8
SA7
SA6
Back
SA5
D18
D1
B31
B1 side
SA4
SA3
of
C18
C1
A31
A1
SA2
PC
SA1
SA0