Plenary, 2008 IEEE-CSIC Symposium, October 12, 2008
THz Bipolar Transistor Circuits:
Technical Feasibility,
Technology Development,
Integrated Circuit Results
Mark Rodwell
University of California, Santa Barbara
Coauthors
E. Lobisser, M. Wistey, V. Jain, A. Baraskar, J. Koo
University of California, Santa Barbara
E. Lind
Lund University
Z. Griffith, J. Hacker, M. Urteaga, D. Mensa, Richard Pierson, B. Brar
Teledyne Scientific Company
rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax
The End is
( ! ) Law) is Near (?)
(ofNear
Moore's
It's a great time to be working on electronics !
Things to work on:
InP HEMTs & HBTs: extend (ft , fmax) to 2-3 THz, build THz ICs
GaN HEMTs: develop V- and W-band power amplifiers
Si MOSFETs: work to keep them scaling past 22 nm
CMOS IC design: build ICs which bury the III-V's
InGaAs MOSFETs: help keep VLSI scaling (maybe)
Scaling for
THz Transistors
Simple Device Physics: Resistance
bulk resistance
R
 bulk  T
A
contact resistance
-perpendicular
R
 contact
A
contact resistance
- parallel
R
 contact
A
W'
  sheet 
3L
Good approximation for contact
widths less than 2 transfer lengths.
Simple Device Physics: Depletion Layers
capacitance
A
C 
T
transit time
T
t
2v
space-charge
limited current
I max 2v
 2 Vapplied  Vdepletion  2 
A
T
V
C
t
I C
where

T
I max Vapplied  Vdepletion  2
Simple Device Physics: Thermal Resistance
Exact
Carslaw & Jaeger 1959
Long, Narrow Stripe
HBT Emitter, FET Gate
1
1
L
Rth 
ln   
Kth L  W  Kth L
cylindrica l heat flow
spherical heat flow
near junction
far from junction
Square ( L by L )
IC on heat sink
1
L
Rth 
sinh 1  
Kth L
W 
1
W 

sinh 1  
KthW
L
Rth 
1
1

4 K th L K th L
planar heat flow spherical heat flow
near surface
far from surface
Simple Device Physics: Fringing Capacitance
C
W
    1 .5  
L
T
parallel - plate
fringing
wiring capacitance
C/L
VLSI power-delay limits
slowly - varying function 
C
 

of
W
/
G
and
W
/
G
L
1
2


 (1 to 3)  
FET parasitic capacitances
C parasitic / L ~ 
FET scaling constraints
Frequency Limits
and Scaling Laws
of (most)
Electron Devices
t  thickness
C  area / thickness
Rtop   contact / area
Rbottom 
 contact
area

PIN photodiode
Rtop
 sheet width
4

Rbottom
length
I max, space-charge-limit  area / thickness

2
power
 length 
T 
 log 

length
 width 
To double bandwidth,
reduce thicknesses 2:1
Improve contacts 4:1
reduce width 4:1, keep constant length
increase current density 4:1
Bipolar
Transistor
Design
Bipolar Transistor Design
We
Tb
t b  T 2 Dn
2
b
Wbc
Tc
t c  Tc 2v sat
Ccb  Ac /Tc
I c ,max  vsat Ae (Vce,operating  Vce,punch-through) / T
2
c
P
T 
LE

 Le 
1  ln  
 We 

Rex  contact /Ae
 We Wbc  contact
 
Rbb  sheet 

 12 Le 6 Le  Acontacts
emitter
length LE 
Bipolar Transistor Design: Scaling
We
Tb
t b  T 2 Dn
2
b
Wbc
Tc
t c  Tc 2v sat
Ccb  Ac /Tc
I c ,max  vsat Ae (Vce,operating  Vce,punch-through) / T
2
c
P
T 
LE

 Le 
1  ln  
 We 

Rex  contact /Ae
 We Wbc  contact
 
Rbb  sheet 

 12 Le 6 Le  Acontacts
emitter
length LE 
Bipolar Transistor Scaling Laws
We
Tb
Changes required to double transistor bandwidth:
parameter
collector depletion layer thickness
base thickness
emitter junction width
collector junction width
emitter contact resistance
current density
base contact resistivity
emitter
Wbc
Tc
length LE 
change
decrease 2:1
decrease
1.414:1
decrease 4:1
decrease 4:1
decrease 4:1
increase 4:1
decrease 4:1
Linewidths scale as the inverse square of bandwidth because thermal constraints dominate.
Thermal Resistance Scaling : Transistor, Substrate, Package
Tsubstrate 
cylindrica l heat flow
spherical flow
planar flow
near junction
for r  Le
for r  DHBT / 2
L 
P  1 1
P  Tsub  D / 2 

ln  e  
  


K InP LE  We  K InP  LE D  K InP 
D2

P
increases
insignific ant
increases quadratica lly
logarithmi cally
variation
if Tsub is constant
 1 1  Pchip
Tpackage    
 4   KCuWchip
junction temperature rise, Kelvin
140 Tsub  40 m  (150 GHz / f clock )
120
Wiring lenghts
total
2000 - HBT CML IC
scale as
100
80
1/bandwidt h.
substrate: cylindrical+spherical regions
60
scales as
substrate: planar region
20
0
100
Power density,
package
40
(bandwidth ) 2 .
200
300
400
500
600
master-slave D-Flip-Flop clock frequency, GHz
700
Thermal Resistance Scaling : Transistor, Substrate, Package
Tsubstrate 
cylindrica l heat flow
spherical flow
planar flow
near junction
for r  Le
for r  DHBT / 2
L 
P  1 1
P  Tsub  D / 2 

ln  e  
  


K InP LE  We  K InP  LE D  K InP 
D2

P
increases
insignific ant
increases quadratica lly
logarithmi cally
variation
if Tsub is constant
 1 1  Pchip
Tpackage    
 4   KCuWchip
junction temperature rise, Kelvin
140 Tsub  40 m  (150 GHz / f clock )
120
Wiring lenghts
2000 - HBT CML IC
Probable
best solution:
scale as
1/bandwidt h.
Thermal Vias ~500 nm below InP subcollector
Power density,
...over full active IC area.
scales as
total
100
80
substrate: cylindrical+spherical regions
60
package
40
substrate: planar region
20
0
100
(bandwidth ) 2 .
200
300
400
500
600
master-slave D-Flip-Flop clock frequency, GHz
700
InP Bipolar Transistor Scaling Roadmap
industry university university appears
→industry 2007-8
feasible
maybe
emitter 512
16
256
8
128
4
64
2
32 nm width
1 m2 access 
base
300
20
175
10
120
5
60
2.5
30 nm contact width,
1.25 m2 contact 
collector 150
4.5
4.9
106
9
4
75
18
3.3
53
36
2.75
37.5 nm thick,
72 mA/m2 current density
2-2.5 V, breakdown
520
850
430
240
730
1300
660
330
1000
2000
1000
480
1400 GHz
2800 GHz
1400 GHz
660 GHz
ft
fmax
power amplifiers
digital 2:1 divider
370
490
245
150
We
Tb
Wbc
Tc
Can we make a 1 THz SiGe Bipolar Transistor ?
InP
emitter 64
2
SiGe
18
1.2
nm width
m2 access 
56
1.4
nm contact width,
m2 contact 
collector 53
36
2.75
15
125
???
nm thick
mA/m2
V, breakdown
ft
fmax
1000
2000
GHz
GHz
Simple physics clearly drives scaling
transit times, Ccb/Ic
→ thinner layers, higher current density
high power density → narrow junctions
base
small junctions→ low resistance contacts
Key challenge: Breakdown
15 nm collector → very low breakdown
(also need better Ohmic contacts)
64
2.5
1000
2000
PAs
1000 1000
GHz
digital 480
480
GHz
(2:1 static divider metric)
Assumes collector junction 3:1 wider than emitter.
Assumes SiGe contacts 2:1 wider than junctions
HBT Design For IC Performance
from charge-control analysis:
Tgate  ( VL / I C )( C je  6Ccbx  6Ccbi )  t f
 ( kT / qI C )( 0.5C je  Ccbx  Ccbi  0.5t f I C / VL )
 Rex ( 0.5Ccbx  0.5Ccbi  0.5t f I C / VL )
 Rbb( 0.5C je  Ccbi  0.5t f I C / VL ).
InP HBT: Status
InP DHBTs: September 2008
400 500
GHz GHz
1000
600
GHz
900
GHz
800
GHz
700
GHz

Teledyne DBHT ( ft  f max ) / 2
125 nm
UIUC DHBT
800
NTT DBHT
max
(GHz)
250 nm
f
popular metrics :
ft or f max alone
ft f max
ft f max
(1 ft  1 f max ) 1
ETHZ DHBT
600
UIUC SHBT
250 nm
UCSB DHBT
400
NGST DHBT
600nm
HRL DHBT
IBM SiGe
200
350 nm
Vitesse DHBT
much better metrics :
power amplifiers :
PAE, associated gain,
mW/ m
low noise amplifiers :
Fmin , associated gain,
digital :
f clock , hence
(Ccb V / I c ),
Updated Sept. 2008
0
0
200
400
600
ft (GHz)
800
1000
( Rex I c / V ),
( Rbb I c / V ),
(τb  τc )
512 nm InP DHBT
500 nm mesa HBT
150 GHz M/S latches
175 GHz amplifiers
Laboratory
Technology
UCSB / Teledyne / GCS
UCSB
500 nm sidewall HBT
DDS IC: 4500 HBTs
20-40 GHz op-amps
Teledyne
Teledyne / BAE
Teledyne / UCSB
Production
( Teledyne )
Z. Griffith
M. Urteaga
P. Rowell
D. Pierson
B. Brar
V. Paidi
ft = 405 GHz
fmax = 392 GHz
Vbr, ceo = 4 V
20 GHz clock
53-56 dBm OIP3 @ 2 GHz
with 1 W dissipation
40
H
mA/m2
10
30
dB
256 nm Generation
InP DHBT
150 nm thick collector
U
21
20
f
10
max
= 780 GHz
t
10
10
10
11
2
3
4
5
12
11
10
20
21
2
mA/m
dB
10
max
1
V
U
f
0
12
10
ce
10
10
10
9
10
H
20
4
0
Hz
70 nm thick collector
30
6
2
f = 424 GHz
0
9
10
8
= 560 GHz
15
10
5
f = 560 GHz
t
324 GHz
Amplifier
0
0
9
10
10
10
11
10
0
12
10
1
2
V
Hz
3
4
ce
60 nm thick collector
40
30
H
30
2
U
mA/m
dB
200 GHz
master-slave
latch design
21
20
10 fmax = 218 GHz
20
10
f = 660 GHz
Z. Griffith, E. Lind
J. Hacker, M. Jones
t
0
9
10
10
10
11
10
Hz
10
12
0
0
1
2
V
ce
3
324 GHz Medium Power Amplifiers in 256 nm HBT
ICs designed by Jon Hacker / Teledyne
Teledyne 256 nm process flowHacker et al, 2008 IEEE MTT-S
Gain (dB), Power (dBm), PAE (%)
20
10
40
Output Power (dBm)
Gain (dB)
Drain Current (mA)
PAE (%)
30
0
20
-10
10
-20
-20
0
-15
-10
-5
Input Power (dBm)
0
5
Current, mA
~2 mW saturated output power
128 / 64 / 32 nm
HBT Technologies
Conventional ex-situ contacts are a mess
THz transistor bandwidths: very low-resistivity contacts are required
textbook contact
with surface oxide
with metal penetration
Interface barrier → resistance
Further intermixing during high-current operation → degradation
Improvements in Ohmic Contacts
128 nm generation requires ~ 4  - μm2 emitter & base resistivities
64 nm generation requires ~ 2  - μm2
Contacts to N-InGaAs*:
Mo
MBE in-situ
0.3 (+/- 0.7)  - μm2
TiW
ex-situ / NH4 pre-clean
~1 to 2  - μm2
variable between process runs
Contacts to P-InGaAs:
Mo
MBE in-situ
Pd/Ti...
ex-situ
below 2.5  - μm2
~4  - μm2
*measured emitter resistance remains higher than that of contacts.
Mo Emitter Contacts: Robust Integration into Process Flow
Proposed Process Integration:
Process Must Change Greatly for 128 / 64 / 32 nm Nodes
control undercut
→ thinner emitter
thinner emitter
→ thinner base metal
Undercutting of emitter ends
{101}A planes: fast
{111}A planes: slow
thinner base metal
→ excess base metal resistance
128 nm Emitter Process: Dry Etched Metal & Semiconductor
a
b
Litho
Cr
pattern
metal
c
SF6/Ar ICP
SiNsidewall
x sidewall
d
e
dry/N
etch
Cl
2 2 ICP
Wetetch
Etch
wet
HCl:H3PO4
BHF
SiO2
TiW
Ti
InGaAs n++
InGaAs n++
InGaAs n++
InP n
InP n
InP n
InP n
InGaAs p++ Base
InGaAs p++ Base
InGaAs p++ Base
InGaAs p++ Base
InGaAs p++ Base
12
20
H
21
10
max
mA/m
f
2
U
20
dB
10
11
10
10
30
10
9
10
Recent Results @ 128 nm emitter width to be submitted
= 560 GHz
15
10
5
f = 560 GHz
t
0
9
10
0
10
10
11
10
Hz
results @ c.a. 200 nm emitter metal width
12
10
0
1
2
V
ce
3
4
Planarization E/B Processes for 64 & 32 nm
Planarization boundary
What about InGaAs HEMTs ?
...& InGaAs MOSFETS ?
InGaAs HEMTs and InGaAs MOSFETs
high-K
gate barrier
Source
Gate
N+ source/ drain
by MBE regrowth
Drain
K Shinohara
sub-22-nm InGaAs MOSFETs being developed for potential use in VLSI
Efforts may: improve understanding HEMT & MOSFET scaling limits
produce process modules which aid THz HEMTs
Key III-V MOSFET scaling limits:
low density of states→limits gm→ Cfringing/gm does not scale
low m* → high well energy → minimum well thickness
Additional HEMT scaling limits:
high access resistance: barriers, recess regions, contacts
limits to sheet concentration from small hetero-barrier energy
HBT Applications
Applications of THz InP HBTs
Mixed-Signal ICs (ADCs, DACs, DDS)
benefit in high-clock-rate ICs with 1k-3k devices
lack of CMOS integration a major limitation
→ Mark Rosker's talk
Precision GHz analog ICs using THz transistors
→ Sanjay Raman's talk , Zach Griffith's talks
mm-Wave Power: 60 GHz & up
GaN threatens, but fmax→ gain → PAE
600-1000 GHz transceiver ICs
for low-volume military / scientific applications
Few-THz Bipolar Transistors
THz InP Bipolar Transistors: can it be done ?
Scaling limits: contact resistivities, device and IC thermal resistances.
62 nm (1 THz ft , 1.5 THz fmax ) scaling generation is feasible.
700 GHz amplifiers, 450 GHz digital logic
Is the 32 nm (1 THz amplifiers) generation feasible ?
THz InP Bipolar Transistors: what would we do with it ?
Mixed-Signal IC Power density & CMOS integration are serious challenges
Precision GHz analog systems
mm-wave power
Sub-mm-wave electronics