Lecture 11:
Sequential
Circuit
Design
Outline






Sequencing
Sequencing Element Design
Max and Min-Delay
Clock Skew
Time Borrowing
Two-Phase Clocking
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
2
Sequencing
 Combinational logic
– output depends on current inputs
 Sequential logic
– output depends on current and previous inputs
– Requires separating previous, current, future
– Called state or tokens
– Ex: FSM, pipeline
clk
in
clk
clk
clk
out
CL
Finite State Machine
11: Sequential Circuits
CL
CL
Pipeline
CMOS VLSI Design 4th Ed.
3
Sequencing Cont.
 If tokens moved through pipeline at constant speed,
no sequencing elements would be necessary
 Ex: fiber-optic cable
– Light pulses (tokens) are sent down cable
– Next pulse sent before first reaches end of cable
– No need for hardware to separate pulses
– But dispersion sets min time between pulses
 This is called wave pipelining in circuits
 In most circuits, dispersion is high
– Delay fast tokens so they don’t catch slow ones.
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
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Sequencing Overhead
 Use flip-flops to delay fast tokens so they move
through exactly one stage each cycle.
 Inevitably adds some delay to the slow tokens
 Makes circuit slower than just the logic delay
– Called sequencing overhead
 Some people call this clocking overhead
– But it applies to asynchronous circuits too
– Inevitable side effect of maintaining sequence
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
5
Sequencing Elements
Flop
Latch
 Latch: Level sensitive
– a.k.a. transparent latch, D latch
 Flip-flop: edge triggered
– A.k.a. master-slave flip-flop, D flip-flop, D register
 Timing Diagrams
clk
clk
– Transparent
D
Q
D
Q
– Opaque
– Edge-trigger
clk
D
Q (latch)
Q (flop)
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
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Latch Design
 Pass Transistor Latch
 Pros
+ Tiny
+ Low clock load
 Cons
– Vt drop
– nonrestoring
– backdriving
– output noise sensitivity
– dynamic
– diffusion input
11: Sequential Circuits
CMOS VLSI Design 4th Ed.

D
Q
Used in 1970’s
7
Latch Design
 Transmission gate
+ No Vt drop
- Requires inverted clock

D
Q

11: Sequential Circuits
CMOS VLSI Design 4th Ed.
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Latch Design
 Inverting buffer
+ Restoring
+ No backdriving
+ Fixes either
• Output noise sensitivity
• Or diffusion input
– Inverted output
11: Sequential Circuits
CMOS VLSI Design 4th Ed.

X
D

Q

D
Q

9
Latch Design
 Tristate feedback
+ Static
– Backdriving risk

X
D

 Static latches are now essential
because of leakage
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
Q


10
Latch Design
 Buffered input
+ Fixes diffusion input
+ Noninverting

X
D

Q


11: Sequential Circuits
CMOS VLSI Design 4th Ed.
11
Latch Design
 Buffered output
+ No backdriving

X
D

 Widely used in standard cells
+ Very robust (most important)
- Rather large
- Rather slow (1.5 – 2 FO4 delays)
- High clock loading
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
Q


12
Latch Design
 Datapath latch
+ smaller
+ faster
- unbuffered input

Q
X
D



11: Sequential Circuits
CMOS VLSI Design 4th Ed.
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Flip-Flop Design
 Flip-flop is built as pair of back-to-back latches


X
D
Q




X
D

Q


11: Sequential Circuits
Q



CMOS VLSI Design 4th Ed.
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Enable
 Enable: ignore clock when en = 0
– Mux: increase latch D-Q delay
– Clock Gating: increase en setup time, skew
Symbol
Multiplexer Design
Clock Gating Design
 en
D
1
Q
0
en
Q
D
 en
1
0
Q
Q
D
en
Flop
D
Flop

Flop
Q
en

D
Latch

Latch
D
Latch

Q
en
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
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Reset
 Force output low when reset asserted
 Synchronous vs. asynchronous

Q
D
reset
Synchronous Reset

Q

reset
D

Q
Q







Asynchronous Reset
Q


Q


reset
reset
D
D






reset
reset

11: Sequential Circuits
Q
reset

reset
D
Flop
Symbol
D
Latch


CMOS VLSI Design 4th Ed.

16
Set / Reset
 Set forces output high when enabled
 Flip-flop with asynchronous set and reset


reset
set
D



Q

set
reset

11: Sequential Circuits

CMOS VLSI Design 4th Ed.
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Sequencing Methods
clk
clk
Combinational Logic
tnonoverlap
Combinational
Logic
1
Combinational
Logic
Latch
2
Latch
1
Half-Cycle 1
tpw
CMOS VLSI Design 4th Ed.
p
Combinational Logic
Latch
p
Latch
Pulsed Latches
p
tnonoverlap
Tc/2
2
Latch
2-Phase Transparent Latches
1
Half-Cycle 1
11: Sequential Circuits
Flop
clk
Flop
Flip-Flops
 Flip-flops
 2-Phase Latches
 Pulsed Latches
Tc
18
Timing Diagrams
Contamination and
Propagation Delays
A
A
tpd
Logic Prop. Delay
tcd
Logic Cont. Delay
tpcq
Latch/Flop Clk->Q Prop. Delay
tccq
Latch/Flop Clk->Q Cont. Delay
tpdq
Latch D->Q Prop. Delay
tcdq
Latch D->Q Cont. Delay
tsetup
Latch/Flop Setup Time
thold
Combinational
Logic
Y
Y
clk
Flop
clk
D
Q
tcd
tsetup
thold
D
tpcq
Q
Latch
D
tccq
clk
clk
tccq
Q
Latch/Flop Hold Time
11: Sequential Circuits
tpd
tsetup
tpcq
D
tcdq
thold
tpdq
Q
CMOS VLSI Design 4th Ed.
19
clk
sequencing overhead
clk
Q1
Combinational Logic
D2
F2
t pd  Tc   tsetup  t pcq 
F1
Max-Delay: Flip-Flops
Tc
clk
Q1
tsetup
tpcq
tpd
D2
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
20
Max Delay: 2-Phase Latches
D1
sequencing overhead
Q1
Combinational
Logic 1
D2
1
Q2
Combinational
Logic 2
D3
L3
pdq
2
L2
 2t 
L1
t pd  t pd 1  t pd 2  Tc 
1
Q3
1
2
Tc
D1
Q1
tpdq1
tpd1
D2
tpdq2
Q2
tpd2
D3
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CMOS VLSI Design 4th Ed.
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Max Delay: Pulsed Latches
D1
sequencing overhead
p
Q1
D2
Combinational Logic
L2
p
L1
t pd  Tc  max  t pdq , t pcq  tsetup  t pw 
Q2
Tc
D1
(a) tpw > tsetup
tpdq
Q1
tpd
D2
p
tpcq
Q1
Tc
tpd
tpw
tsetup
(b) tpw < tsetup
D2
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
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Min-Delay: Flip-Flops
clk
F1
tcd  thold  tccq
Q1
CL
clk
F2
D2
clk
Q1 tccq
D2
11: Sequential Circuits
tcd
thold
CMOS VLSI Design 4th Ed.
23
Min-Delay: 2-Phase Latches
1
L1
tcd 1,tcd 2  thold  tccq  tnonoverlap
1
L2
D2
Paradox: hold applies
twice each cycle, vs.
only once for flops.
tnonoverlap
tccq
2
Q1
D2
11: Sequential Circuits
CL
2
Hold time reduced by
nonoverlap
But a flop is made of
two latches!
Q1
tcd
thold
CMOS VLSI Design 4th Ed.
24
Min-Delay: Pulsed Latches
p
Q1
CL
p
D2
p
L2
Hold time increased
by pulse width
L1
tcd  thold  tccq  t pw
tpw
thold
Q1 tccq
tcd
D2
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CMOS VLSI Design 4th Ed.
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Time Borrowing
 In a flop-based system:
– Data launches on one rising edge
– Must setup before next rising edge
– If it arrives late, system fails
– If it arrives early, time is wasted
– Flops have hard edges
 In a latch-based system
– Data can pass through latch while transparent
– Long cycle of logic can borrow time into next
– As long as each loop completes in one cycle
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
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Time Borrowing Example
1
2
Combinational Logic
Borrowing time across
half-cycle boundary
Combinational
Logic
Borrowing time across
pipeline stage boundary
2
Combinational Logic
Latch
(b)
Latch
1
1
Latch
2
Latch
(a)
Latch
1
Combinational
Logic
Loops may borrow time internally but must complete within the cycle
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
27
How Much Borrowing?
D1
L1
tborrow
T
 c   tsetup  tnonoverlap 
2
1
2
Q1
Combinational Logic 1
D2
L2
2-Phase Latches
Q2
1
Pulsed Latches
2
tborrow  t pw  tsetup
tnonoverlap
Tc
Tc/2
Nominal Half-Cycle 1 Delay
tborrow
tsetup
D2
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
28
Clock Skew
 We have assumed zero clock skew
 Clocks really have uncertainty in arrival time
– Decreases maximum propagation delay
– Increases minimum contamination delay
– Decreases time borrowing
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
29
Skew: Flip-Flops
sequencing overhead
Q1
F1
t pd  Tc   t pcq  tsetup  tskew 
clk
Combinational Logic
D2
F2
clk
Tc
clk
tcd  thold  tccq  tskew
tpcq
Q1
tskew
tpdq
tsetup
D2
F1
clk
Q1
CL
D2
F2
clk
tskew
clk
thold
Q1 tccq
D2
11: Sequential Circuits
tcd
CMOS VLSI Design 4th Ed.
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Skew: Latches
Q1
Combinational
Logic 1
D2
1
Q2
Combinational
Logic 2
D3
Q3
pdq
1
sequencing overhead
tcd 1 , tcd 2  thold  tccq  tnonoverlap  tskew
tborrow 
2
L3
 2t 
D1
L1
t pd  Tc 
1
L2
2-Phase Latches
2
Tc
  tsetup  tnonoverlap  tskew 
2
Pulsed Latches
t pd  Tc  max  t pdq , t pcq  tsetup  t pw  tskew 
sequencing overhead
tcd  thold  t pw  tccq  tskew
tborrow  t pw   tsetup  tskew 
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
31
Two-Phase Clocking
 If setup times are violated, reduce clock speed
 If hold times are violated, chip fails at any speed
 In this class, working chips are most important
– No tools to analyze clock skew
 An easy way to guarantee hold times is to use 2phase latches with big nonoverlap times
 Call these clocks 1, 2 (ph1, ph2)
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
32
Safe Flip-Flop
 Past years used flip-flop with nonoverlapping clocks
– Slow – nonoverlap adds to setup time
– But no hold times
 In industry, use a better timing analyzer
– Add buffers to slow signals if hold time is at risk


X
D

Q


11: Sequential Circuits
Q



CMOS VLSI Design 4th Ed.
33
Adaptive Sequencing
p
X
 Designers include timing margin
ERR
– Voltage
D
Q
– Temperature

– Process variation
D
Q
– Data dependency
X
– Tool inaccuracies
ERR
 Alternative: run faster and check for near failures
– Idea introduced as “Razor”
• Increase frequency until at the verge of error
• Can reduce cycle time by ~30%
p
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
34
Summary
 Flip-Flops:
– Very easy to use, supported by all tools
 2-Phase Transparent Latches:
– Lots of skew tolerance and time borrowing
 Pulsed Latches:
– Fast, some skew tol & borrow, hold time risk
11: Sequential Circuits
CMOS VLSI Design 4th Ed.
35