Xilinx Development
Software Design Flow
on Foundation M1.5
Design Flow
1
Design Entry in schematic, ABEL, VHDL,
and/or Verilog. Vendors include Synopsys,
Aldec (Xilinx Foundation), Mentor,
Cadence, Viewlogic, and 35 others.
2
Implementation includes Placement &
Routing and bitstream generation using
Xilinx’s M1 Technology. Also, analyze timing,
view layout, and more.
M1 Technology
Download directly to the Xilinx
hardware device(s) with
unlimited reconfigurations* !!
3
XC4000 XC4000
*XC9500 has 20,000 write/erase cycles
XC4000
Design Tools
 Standard CAE entry and verification tools
 Xilinx Implementation software implements the
design
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The design is optimized for best performance and mini size
Graphical User Interface and Command Line Interface
Easy access to other Xilinx programs
Manages and tracks design revisions
Foundation
or Alliance
Functional Simulation
Design
Entry
Schematic, State Mach., HDL
Code, LogiBLOX, CORE Gen
Simulator
Back Annotation
Verification
M1 Design Manager
Xilinx
Design Implementation
Static Timing Analysis,
In-Circuit Testing
Multi-Source Integration
Mixed-Level Flows
HDL
Schematic
Existing
Designs
Cores
 Enables multiple sources
and multiple EDA vendors
in the same flow
Design Source
Integration
Standards
Based
EDIF
VHDL
Verilog
SDF
Knowledge
Driven
Implementation
Check Point
Verification
 Allows team development
 Reduces design source
translations
 Design the way you are
used to
 Enables rapid, accurate
iterations
 Works well within existing
ASIC flows

Facilitates Design Reuse
3rd Party Support & Libraries
 Xilinx 3rd Party Design Entry & Simulation Support
— Synopsys, Cadence, Mentor Graphics, Aldec (Foundation)
— Viewlogic, Synplicity, OrCad, Model Technologies, Synario,
Exemplar and others supply libs & interfaces
— Industry standard file formats:
– VHDL, Verilog, and EDIF netlist formats
– SDF Standard Delay files
– VITAL library support
 Xilinx Libraries
— Optimized components for use in any Xilinx FPGA or CPLD
— Wide range of functions
– Comparators, Arithmetic functions, memory
– DSP and PCI interfaces
— Easy to use with ABEL, VHDL, Verilog, schematic entry
Libraries, Macros & Attributes
 Libraries are common design sets for all design entry tools
(eg. text, schematic, Foundation, Synopsys, Viewlogic, etc.)
— Unified Libraries:
– Boolean functions, TTL,
Flip-Flops, Adders,
RAM, small functions
— LogiBlox Libraries:
– Variable size blocks of
adders, registers, RAM,
ROM, etc.
– Properties defined as
attributes
 Library “interfaces” are specific to each front end
 Attributes are library element properties
 Online “Libraries Guide” has full listings and descriptions
Foundation Express 1.5 Overview
 Easy to use, yet powerful
 Based on Industry Std, not proprietary languages
 Features:
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Schematic (partnership with Aldec)
IEEE VHDL, Verilog, ABEL
State Diagram Editor
Interactive Simulation
Exclusive partnership with Synopsys, the synthesis leader
Synopsys
Aldec
Xilinx
Foundation Project Manager
 Integrates all tools into one environment
Schematic Entry
ABEL and VHDL Text Entry
 From schematic menu
(or via HDL Editor),
select Hierarchy -> New
Symbol Wizard… to
create symbol.
 Select HDL Editor &
Language Assistant to
learn by example, then
define block.
 Synthesize to EDIF.
1
5
4
2
3
State Machine Graphical Editor
Graphical editor synthesizes into ABEL or VHDL code
LogiBLOX
Simulation-Easy to Use & Learn
• Generate stimulus
easily and quickly
– Keyboard toggling
– Simple clock stimulus
– Custom formulas
• Easy debugging
– Waveform viewer
– Signals easily added
and removed
– Simulator access from
schematic
– Color-coded values on
schematic
• Script Editor
Xilinx-Express Design Flow
DSP COREGen
& LogiBLOX
Module Generator
XNF
.NGO
VHDL
Verilog
Behavioral Simulation Models
.VEI
.VHI
HDL Editor
VHDL
Verilog
State Diagram
Editor
.V
.VHD
Schematic
Capture
EDIF
XNF
Gate Level
Simulator
VHDL
Verilog
Timing
Requirements
Express
EDIF/XNF
.UCF
Reports
.XNF
Foundation Design Entry Tools
Xilinx Implementation Tools
Reports
EDIF
BIT
JDEC
SDF
VHDL
Verilog
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S
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T
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Express Input and Output
 Input files may be VHDL or Verilog format
— Mixed Verilog/VHDL modules are
accepted
— Schematics may also be used, but
should not be input into Express
— Schematic files in XNF or EDIF
format will be merged into the
design in Xilinx Design Manager
 Output netlists are in XNF
format
VHDL
Verilog
Timing
Requirements
Express
.XNF
Reports
 Timing Specifications may be
specified in Express
— Timing Specifications are not used during Synthesis
— Timing Specifications can be included in the output
netlist
Express Design Process
2
3
1
{
2
1. Analyze - Syntax check
2. Implement - Create generic logic design (Elaborate)
3. Enter constraints and options
4. Synthesize - Optimize the design for specific device
5. Export XNF Netlist
6. Implement layout with Xilinx Design Manager
4
M1 Design Manager
 Manages
design data
 Access
reports
 Supports
CPLDs,
FPGAs
Flow Engine
Timing Analyzer
Floorplanner
PROM File Formmater
Hardware Debugger
EPIC Design Editor
JTAG Programmer
Terminology
 Project
— Source file; has a defined working directory and family
 Version
— A Xilinx netlist translation of the schematic
— Multiple Versions result from iterative schematic changes
 Revision
— An implementation of a Xilinx netlist
— Multiple revisions typically result from different options
 Part type
— Specified at translation; can be changed in a new revision
Logical Design Files
 Logical Design Files describe your design, and are
composed of logical components
— Typically a netlist, generated by Schematic Capture or Synthesis
— Composed of Boolean Gates, FIFOs, RAMs
 Netlist input to XACT-Step M1 is in EDIF format
— XNF files are also accepted
 EDIF format files are translated to (Native Generic
Design) NGD format
— NGD files have varying extensions
— Ex: NGD, NGM, NGA, NGO
 NGD files can be translated to other formats for
simulation
Physical Design Files
 Physical design files are composed of
components found in a Xilinx FPGA such as
look-up tables and flip-flops
— Physical design files have .ncd extension
— Map creates an NCD file from an NGD file
— NCD files contain varying pieces of information
– Mapping, placement, and routing tools each concatenate
data to the bottom of the NCD file
.XNF or EDIF netlist
UCF
User Constraint File
NGDBUILD
Flatten Hierarchical Design
.NGD
MAP
M1-Based
Design Flow
Logical to Physical translation
Groups LUTs and FFs Into CLBs
.NCD
.PCF
TRCE
Static Timing Estimates
TRCE
Static Timing Analysis
PAR
BITGEN
Layout of Physical Design
Routes Physical Design
Generates configuration file
.NCD
.BIT
Design Flow Programs (1)
 NGDBUILD
— Merges hierarchical EDIF or XNF files into one hierarchical
file on the Flow Engine
— Creates internal netlist .ngd(Native Generic Design) files
— Contains logical components: combinatorial gates, RAMS,
flip-flops, etc.
 MAP
— Maps logical components to physical components found in
Xilinx FPGA: look up tables, Flip-Flops, three state buffers,
etc into the device
— Packs physical components into COMPS
— Creates internal .ncd (Native Circuit Design) file
Translate
Map
Place & Route
Configure
Design Flow Programs (2)
 TRCE
— Analyzes Timing
–
Use before PAR to analyze constraints
 PAR
— Places COMPS on FPGA
— Routes the FPGA
 TRCE
— Analyzes Timing
–
Use after PAR to check delays
 NGDANNO
— Back-annotate timing delays for Simulation
 BITGEN
— Create file to configure FPGA