CEC 222 Digital Electronics Lab
Spring 2015
Lab 8: Debouncing a SPDT Switch
Learning Objectives:

Introduction to transparent latches.

Develop an appreciation of the challenges related to interfacing slow mechanical devices (e.g., a switch)
with high speed digital circuits.
Lab Overview:
A single pole double throw (SPDT) switch (see Figure 1) is a mechanical device and as such responds much
slower than an electronic circuit. When a switch is opened or closed the mechanical contacts do not make or
break the connection instantaneously, but can
"bounce" between open and closed, thus
making several transitions. The three terminals
of the SPDT switch shown in Figure 1 are
common (C), normally closed (NC), and
normally open (NO).
If you were to use a mechanical switch to
Figure 1 A single pole double throw (SPDT) switch.
increment a counter (e.g., count people going through a turnstile), a single closure of the switch could increment
the counter many times resulting in an incorrect result. In this lab we will use the logic analyzer to look at switch
bounce, and use an SR latch to debounce the mechanical switch. The extra credit experiment considers the
problem of debouncing a single pole single throw (SPST) switch.
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Lab 8: Debouncing a SPDT Switch
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CEC 222 Digital Electronics Lab
Spring 2015
Pre-Lab (10%)
Task 1.
Task 2.
Complete the state-transition table below for a SR (i.e., Set-Reset) latch.
S
R
Q
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Q+
1
Derive the next-state equation for the SR latch
+
Q = ___________________________
0
1
00
01
11
10
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Lab 8: Debouncing a SPDT Switch
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CEC 222 Digital Electronics Lab
Spring 2015
Experiments (90%)
EXPERIMENT 1.
MECHANICAL SWITCH BOUNCE
In this initial experiment you will be observing the mechanical bounce of a SPDT switch using the logic
analyzer (LA) functionality within your analog discovery.
Step 1.a: Build the circuit and connect it to the LA

Remember to TURN OFF
the power when working
on your circuit!!
Build the circuit shown in Figure 2 on your
breadboard.

Use the Analog Discovery to provide Vcc (=5V)
and GND (see Lab 2, Experiment 1, Step 1a for
a reminder).
 Start Waveforms, click on Voltage icon, and
turn on the power supply.

Connect the normally closed (NC) terminal to
Figure 2 A SPDT switch with pull-down resistors
LA channel 0 (Pink - top) and the normally
open (NO) terminal to LA channel 1 (Green - top). Refer to Analog Discovery Connections.

Start the Logic Analyzer software (
) and display only DIO channels 0 (Name it NC/S) and 1 (Name it
NO/R). Right click and select “Edit properties” to change the names.
 Set the time Base to 1 ms/div.
Question 1. What are the “resting” logic levels of NC/S and NO/R?
NC/S = ____________ and NO/R = ____________
Step 1.b: Capture the switch bounce

In the LA window click on the
icon, then press the SPDT switch, and then quickly click on the
icon to capture the transition on the NC/S terminal (and the transition on the NO/R terminal).
 That approach did not work because the events are happening much faster than a human can
respond. By the time you pressed the SPDT switch and tried to stop the LA data collection the
transition from high to low on the NC/S terminal had long gone.
YOUR NAME(S)
Lab 8: Debouncing a SPDT Switch
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CEC 222 Digital Electronics Lab
Spring 2015
 In order to observe this transition you need to have the logic analyzer
stop “shortly” after the transition. Making the logic analyzer stop
after observing a desired pattern is called triggering. To trigger the
logic analyzer on the high to low transition of the NC/S terminal right
click on the NC/S signal and select Falling Edge triggering.
 Click on the
icon to arm the data collection then push the
SPDT switch to generate the transition.
Task 3.
Capture a screenshot of the LA showing the transitions on both the NC/S and NO/R terminals.
You may want to try this a few times to maximize the number of bounces. You might want to set your
timebase to less than 1ms in order to “zoom-in” on the bouncing.
Figure 3 Logic analyzer screenshot of mechanical switch bouncing
Question 2. Referring to Figure 3, approximately how many “bounces” did you see on the NC/S and on the
NO/R terminals, respectively?
NC/S bounces = __________________
NO/R bounces = ________________
Question 3. Referring to Figure 3, what is the approximate time interval (in ms) between the first transition
(likely a bounce) on the NC/S terminal and the first transition and on the NO/R terminal?
Time interval = _________________ ms

Leave your circuit intact as you will need it for the next experiment. TURN OFF THE POWER!!!
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Lab 8: Debouncing a SPDT Switch
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CEC 222 Digital Electronics Lab
EXPERIMENT 2.
Spring 2015
DEBOUNCING A SPDT SWITCH WITH A SR LATCH
In this next experiment you will be debouncing the SPDT switch
which you constructed in Experiment 1. This will be accomplished by
realizing a transparent SR latch built from NOR gates.
7402
Step 2.a: Build the debounce circuit.

Add a 7402 (quad NOR gate) to your breadboard and make the
connections as shown in the schematic of Figure 4.
 Remember to connect GND (pin 7) and Vcc (pin 14) as
these are not shown in the schematic.
10 k
 The pin numbers for the 7402 are also given in Figure 4
Vcc
S
2
3
NC
C
10 k
NO
5
6
1
4
Q
R
Figure 4 Schematic for debouncing a SPDT switch using a SR latch

Connect channel 2 (purple) of the LA to the output of the latch (i.e., 7402 pin 4) and name it Q.
Step 2.b: Capture the signals

Set the LA to trigger on the high to low (falling edge) transitions of the signal Q.
 All of the other triggers should be don’t care (i.e., “X”).
 The time Base should start at 1 ms/div. Zoom-in afterwards if needed.
Task 4.
Repeat the process from Task 3 and insert your screenshot into Figure 5. Now you should now
have three signals: NC/S, NO/R, and Q. Be sure to include the transition on the NC/S signal in your screen
capture.
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Lab 8: Debouncing a SPDT Switch
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CEC 222 Digital Electronics Lab
Spring 2015
Figure 5 Logic analyzer screenshot of debounced signal
Question 4. Where/when did the output (i.e., Q) of the SR latch transition from high to low and why did it
transition where it did (HINT: Refer to the state-transition table from the pre-lab)?
_____________________________________________________________________________________
___________________________________________________________________________________________
___________________________________________________________________________________________

Increase the time base to allow you to capture both the falling and rising transitions on the output Q of
the SR latch.
 You will want to press and release the SPDT switch very quickly – try to minimize the interval.
Task 5.
Capture a screenshot of the LA showing both transitions on Q and insert it into Figure 6.
Figure 6 Logic analyzer screenshot of both transitions on Q
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Lab 8: Debouncing a SPDT Switch
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CEC 222 Digital Electronics Lab
Spring 2015
Question 5. Referring to Figure 6, what is the approximate time interval (in ms) between the falling and
rising transitions on Q?
Time interval = _____________ ms
Question 6. Did your circuit eliminate the bouncing? ________
Optional Exercise(s) (+10% Extra Credit)
EXPERIMENT 3.
DEBOUNCING A SPST SWITCH
A single-pole single-throw (SPST) switch is a very common low-cost
mechanical switch and often used in home lighting applications.
Question 7. Could you, with minor modifications, use your SR latch circuit
to debounce a SPST switch?
If so explain how:
___________________________________________________________________________________________
___________________________________________________________________________________________
_______________________________________________________________________________
If not, explain why not:
___________________________________________________________________________________________
___________________________________________________________________________________________
_______________________________________________________________________________
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Lab 8: Debouncing a SPDT Switch
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