BACHELOR DEGREE IN
TELECOMMUNICATIONS
3GM1-3GT4
Digital Circuits and Systems (CSD)
26/06/2012
Francec Robert/Josep Jordana
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Third individual test. Grades will be available on Friday, 29th June.
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Questions about the exam: Instructors’ office time.
1- This is a block diagram corresponding to a serial transmitter of a UART (Universal
Asynchronous Receiver Transmitter).
[3P]
a) Indicate the modules corresponding to the datapath. Justify your response.
b) Indicate the name of the control signals and the status signals. Justify your
response.
2- Indicate the frequency of the CLK signal of the following frequency divider in order to
obtain the output frequencies of 0.02 Hz, 1 kHz and 1 MHz. Justify your response. [2P]
3- Scketch the block diagram of a bike computer that only wants to measure distance and
instantaneous speed with 8 bits of resolution and using only two seven segment
displays.
a) Explain and draw the modules involved in the design.
b) Draw and indicate how the state diagram of this control unit works.
c) Suppose that Distance <=”11100101” and speed <=”11001110”. Explain
the timing diagram of your design.
[3P]
4- Draw the timing diagram of a debouncing circuit and its state diagram. Explain how it
works.
[2P]