Sequential Logic
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
EE415 VLSI Design
Project Presentations
What to include in presentation?
•Reason for choosing the design
•Final/Intended application
•Design constraints
•What it does/How it works
•Simulations!, Simulations!!, Simulations!!!
•Layout
•Post-layout simulations!
•Achieved goal? Unexpected glitches? Future work
•Contrast proposed schedule with actual schedule
EE415 VLSI Design
Sequential Logic
Inputs
Outputs
COMBINATIONAL
LOGIC
Current State
Registers
Q
D
CLK
2 storage mechanisms
• positive feedback
• charge-based
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Next state
Meta-Stability
Gain should be larger than 1 in the transition region
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Mux-Based Latches
Negative latch
(transparent when CLK= 0)
1
D
0
Q
0
CLK
Q  Clk  Q  Clk  In
EE415 VLSI Design
Positive latch
(transparent when CLK= 1)
D
1
CLK
Q  Clk  Q  Clk  In
Q
Mux-Based Latch
CLK
QM
CLK
QM
D
CLK
CLK
NMOS only
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Non-overlapping clocks
Mux-Based Latch
CLK
Q
CLK
D
CLK
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Writing into a Static Latch
Use the clock as a decoupling signal,
that distinguishes between the transparent and opaque states
CLK
CLK
Q
CLK
D
D
CLK
D
CLK
Converting into a MUX
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Forcing the state
(can implement as NMOS-only)
Reduced Clock Load
Master-Slave Register
CLK
D
T1
CLK
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CLK
I1
I2
T2
CLK
I3
I4
Q
Avoid Clock Overlap
X
CLK
CLK
Q
D
A
B
CLK
CLK
(a) Schematic diagram
CLK
CLK
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(b) Overlapping clock pairs
Storage Mechanisms
Dynamic (charge-based)
Static
CLK
CLK
Q
D
Q
CLK
CLK
D
Very fast
CLK
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Was popular, now too risky
Making a Dynamic Latch
Pseudo-Static
CLK
D
D
CLK
Weak inverter
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SR-Flip Flop
S
Q
S
Q
R
Q
S
R
Q
Q
0
1
0
1
0
0
1
1
Q
1
0
0
Q
0
1
0
S
R
Q
Q
1
0
1
0
1
1
0
0
Q
1
0
1
Q
0
1
1
Q
R
Forbidden State
S
Q
S
R
R
Q
Q
Q
Forbidden State
EE415 VLSI Design
Cross-Coupled NOR
Added clock
Cross-coupled NORs
S
VDD
Q
M2
M4
Q
Q
R
Q
•Transistors M5-M8 are
CLK
M6
S
M5
wider to switch the state
This is not used in datapaths any more,
but is a basic building memory cell
EE415 VLSI Design
M1
M3
M8
CLK
M7
R
Sizing Issues
2.0
3
Q
S
W = 0.5 m m
2
W = 0.6 m m
W = 0.7 m m
Volts
Q (Volts)
1.5
1.0
1
W = 0.8 m m
0.5
0.0
2.0
2.5
3.0
W/L 5 and 6
3.5
4.0
(a)
Output voltage dependence
on transistor width
EE415 VLSI Design
0
W = 1m m
W = 0.9 m m
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
time (ns)
(b)
Transient response
For various W/L 5 and 6
Naming Conventions

In our text:
» a latch is level sensitive
» a register is edge-triggered

There are many different naming
conventions
» For instance, many books call edgetriggered elements flip-flops
» This leads to confusion however
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Latch versus Register

Latch
stores data when
clock is low

Register
stores data when
clock rises
D Q
D Q
Clk
Clk
Clk
Clk
D
D
Q
Q
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Falls with data
Falls with clock
Latch-Based Design
• N latch is transparent
when f = 0
• P latch is transparent
when f = 1
f
N
Latch
Logic
Logic
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P
Latch
Master-Slave
(Edge-Triggered) Register
Two opposite latches trigger on edge
Also called master-slave latch pair
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Master-Slave Register
Multiplexer-based latch pair
I2
D
T2
I3
I5
T4
I4
T3
QM
I1
CLK
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T1
I6
Q
Timing Definitions
Set-up and hold times are needed to produce a stable output
CLK
t
tsu
D
D
thold
DATA
STABLE
Q
CLK
t
tc 2
Q
Register
q
DATA
STABLE
t
Propagation delay time affects the clock period
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Characterizing Timing
tD 2
D
Q
Clk
tC 2
Q
Clk
Q
Register
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D
Q
tC 2
Q
Latch
Maximum Clock Frequency
FF’s
f
LOGIC
tp,comb
tclk-Q + tp,comb + tsetup = T
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Minimum clock period
decides - the maximum
operating frequency of
a sequential circuit
Also:
tcdreg + tcdlogic > thold
tcd: contamination delay =
minimum delay
Clk-Q Delay
2.5
CLK
Volts
D Q
1.5
D
0.5
2 0.5
0
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tc 2
q(lh)
tc 2
Clk
q(hl)
Q
0.5
1
1.5
time, nsec
2
2.5
Timing of Master-Slave Register
In the multiplexer-based latch pair
assume that propagation delays of
inverters and transmission gates
are tpd_inv and tpd_tx
I2
D
T2
I3
I5
T4
I4
T3
QM
I1
T1
CLK
The setup time states how long before the rising edge of CLK data D must
be stable. D has to propagate through I1, T1, I3, and I4 before the rising edge
of CLK, so
tsetup=3 tpd_inv+tpd_tx
The propagation delay is the time to propagate signal from QM to Q. Since
the output I4 is valid before the rising edge of the clock, so tc-q=tpd_tx+tpd_inv
The hold time (time for the input to be stable after rising edge of the clock)
is 0 since D and clock are delayed by the same amount before reaching the
T1 gate, so a change of D after rising edge of the clock will reach T1 after it is
shut down and will not affect its output.
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I6
Q
Setup Time
=
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=
Output failure
More Precise Setup Time
Setup and hold times
defined when delay
increases by 5%
delay
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Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
CN
TG1
D
Inv2
SM
D1
QM
Clk-Q Delay
Inv1
CP
TClk-Q
TSetup-1
Data
Time
Clock
TSetup-1
t=0
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Time
Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
CN
TG1
D
Inv2
SM
D1
QM
Clk-Q Delay
Inv1
CP
TClk-Q
TSetup-1
Data
Time
Clock
TSetup-1
t=0
EE415 VLSI Design
Time
Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
CN
TG1
D
Inv2
SM
D1
QM
Clk-Q Delay
Inv1
CP
TClk-Q
TSetup-1
Data
Clock
TSetup-1
t=0
EE415 VLSI Design
Time
Time
Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
CN
TG1
D
Inv2
SM
D1
Clk-Q Delay
QM
Inv1
TClk-Q
CP
TSetup-1
Data
Clock
TSetup-1
t=0
EE415 VLSI Design
Time
Time
Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
CN
TG1
D
Inv2
SM
D1
Clk-Q Delay
TClk-Q
QM
Inv1
CP
TSetup-1
Data
Clock
TSetup-1
t=0
EE415 VLSI Design
Time
Time
Setup/Hold Time Illustrations
Hold-1 case
CN
TG1
SM
D1
D
Inv2
Clk-Q Delay
QM
Inv1
CP
0
TClk-Q
THold-1
Clock
Data
THold-1
t=0
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Time
Time
Setup/Hold Time Illustrations
Hold-1 case
CN
TG1
SM
D1
D
Inv2
Clk-Q Delay
QM
Inv1
CP
0
TClk-Q
THold-1
Clock
Data
THold-1
t=0
EE415 VLSI Design
Time
Time
Setup/Hold Time Illustrations
Hold-1 case
CN
TG1
SM
D1
D
Inv2
Clk-Q Delay
QM
Inv1
CP
0
TClk-Q
THold-1
Clock
Data
THold-1
t=0
EE415 VLSI Design
Time
Time
Setup/Hold Time Illustrations
Hold-1 case
CN
TG1
SM
D1
D
Inv1
Inv2
Clk-Q Delay
QM
TClk-Q
CP
0
THold-1
Clock
Data
THold-1
t=0
EE415 VLSI Design
Time
Time
Setup/Hold Time Illustrations
Hold-1 case
CN
TG1
SM
D1
D
Inv2
Clk-Q Delay
QM
TClk-Q
Inv1
CP
0
THold-1
Clock
Data

THold-1
t=0
EE415 VLSI Design
Time
Time
Other Latches/Registers:
CLK
VDD
VDD
M2
M6
M4
CLK
M8
X
D
CLK
M3
M1
Master Stage
2
C MOS
Q
CL1
CLK
M7
CL2
M5
Slave Stage
“Keepers” can be added to make circuit pseudo-static
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Insensitive to Clock-Overlap
0
VDD
VDD
VDD
VDD
M2
M6
M2
M6
M4
0
M8
X
D
Q
X
D
1
M1
M5
1
M1
(a) (0-0) overlap
CLK and C L K  0 at the same time
M3
Q
CLK
VDD
VDD
M2
M6
M4
CLK
M8
CLK
M7
X
D
CLK
M3
M1
CL1
M5
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Master Stage
Slave Stage
M7
M5
(b) (1-1) overlap
Q
CL2
CLK and C L K  1 at the same time
Other Latches/Registers: TSPC
VDD
VDD
VDD
VDD
Out
In
CLK
CLK
In
CLK
CLK
Out
Positive latch
(transparent when CLK= 1)
Negative latch
(transparent when CLK= 0)
Only single phase clocks are used. When f is high the latch is in the
evaluate mode. When f is low the latch is in hold-mode.
EE415 VLSI Design
Including Logic in TSPC
VDD
VDD
VDD
In1
PUN
VDD
In2
Q
In
CLK
CLK
PDN
Q
CLK
CLK
In1
In2
Example: logic inside the latch
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AND latch
TSPC Register
VDD
M3
CLK
VDD
VDD
M6
M9
Y
D
CLK
M2
M1
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X
CLK
M5
M4
Q
Q
CLK
M8
M7
Master-Slave Flip-flops
VDD
VDD
f
D
f
D
f
(a) Positive edge-triggered D flip-flop
D
f
VDD
f
VDD
D
(c) Positive edge-triggered D flip-flop
using split-output latches
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VD D
D
f
f
D
f
f
VDD
VDD
f
Y
X
VDD
VDD
(b) Negative edge-triggered D flip-flop
Pulse-Triggered Latches
An Alternative Approach
Ways to design an edge-triggered sequential cell:
Master-Slave
Latches
L1
Data
Pulse-Triggered
Latch
L2
D Q
D Q
Clk
Clk
L
Data
Clk
D Q
Clk
Clk
Need to generate the glitch pulse
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Pulsed Latches
VDD
VDD
M3
M6
CLK
VDD
Q
D
CLKG
M2
CLKG
M1
MP
M5
MN
M4
(a) register
(b) glitch generation
CLK
CLKG
(c) glitch clock
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CLKG
X
Pulsed Latches
Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :
CLK
P1
P3
x
M6
M3
D
M2
M1
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P2
CLKD
M5
M4
Q
Hybrid Latch-FF Timing
Data not properly
captured due to
insufficient hold time
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CLK
Reference
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b
CLK
CLK
log
REG
REG
CLK
REG
CLK
Out
REG
log
REG
b
REG
CLK
a
REG
a
REG
Pipelining
CLK
CLK
Pipelined
Out
Latch-Based Pipeline
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Non-Bistable Sequential Circuits─
Schmitt Trigger
V OH
Vou t
In
Out
•VTC with hysteresis
V OL
•Restores signal slopes
VM–
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VM+
Vi n
Noise Suppression using
Schmitt Trigger
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CMOS Schmitt Trigger
VDD
M2
Vin
M4
Vout
X
M1
M3
These transistors resist
the change in the X signal
Move switching threshold
of the first inverter
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CMOS Schmitt Trigger
Increasing kn/kp ratio decreases the logical switching threshold
If Vin=0 the Vout (connected to M4) is also zero
So effectively the input is connected to M2 and M4 in parallel
This increases kp and the switching threshold
V DD
If Vin=0 the situation is reversed
and kn increases reducing the
V
switching threshold
M2
X
in
M1
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M4
Vout
M3
Schmitt Trigger Simulated VTC
2.5
2.5
2.0
2.0
Vout(V)
Vout(V)
VM1
1.5
1.0
1.5
1.0
VM2
k=1
k=3
0.5
0.0
0.0
k=2
0.5
0.5
1.0
1.5
Vin (V)
2.0
2.5
Voltage-transfer characteristics with hysteresis.
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k=4
0.0
0.0
0.5
1.0
1.5
Vin (V)
2.0
2.5
The effect of varying the ratio of the
PMOS device M4. The width is k* 0.5m m.
CMOS Schmitt Trigger (2)
With input low and output high
X is charged to VDD –Vth
M2 is cutoff until the input is
larger than VX +Vth
With output being pulled down
M5 is cut off and the output
transition is very rapid
This delays transition from high
to low values on the output.
Symmetrical analysis can be
performed for low to high output
transition
EE415 VLSI Design
VDD
M4
M6
M3
In
Out
M2
X
M1
M5
VDD
Multivibrator Circuits
R
S
Bistable Multivibrator
flip-flop, Schmitt Trigger
T
Monostable Multivibrator
one-shot
Astable Multivibrator
oscillator
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Transition-Triggered Monostable
In
DELAY
td
EE415 VLSI Design
Out
td
Monostable Trigger (RC-based)
VDD
R
In
A
B
Out
(a) Trigger circuit.
C
RC delay regulates the
width of the generated
pulse
In
B
VM
Out
t
t1
EE415 VLSI Design
(b) Waveforms.
t2
Astable Multivibrators (Oscillators)
0
1
2
N-1
Ring Oscillator
V1
V3
V5
V (Volt)
5.0
3.0
1.0
-1.0
0
1
2
3
4
5
t (nsec)
simulated response of 5-stage oscillator
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Relaxation Oscillator
Out1
Out2
I2
I1
R
C
Int
T = 2 (log3) RC
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Voltage Controller Oscillator (VCO)
VDD
VDD
M6
M4
Schmitt Trigger
restores signal slopes
M2
In
M1
Iref
Vcontr
Iref
M3
M5
Current Iref is a quadratic function
of Vcontr
tpH L (nsec)
6
4
This effects the delay time
2
0.0
0.5
EE415 VLSI Design
Current starved inverter
1.5
Vcontr (V)
2.5
propagation delay as a function
of control voltage
Differential Delay Element and VCO
in 2
V o2
v3
V o1
v1
in 1
v2
v
4
two stage VCO
V ctrl
3.0
delay cell
2.5
V1 V2 V3 V4
2.0
1.5
1.0
0.5
0.0
2 0.5
0.5
1.5
2.5
3.5
time (ns)
EE415 VLSI Design
simulated waveforms of 2-stage VCO
JK- Flip Flop
J
S
Q
Q
f
K
R
Q
Q
S R
Q Q
1 1
0 1
Q Q
1 0
1 0
0 0
0 1
1 1
Jn
Kn
Qn+1
0
0
1
1
0
1
0
1
Qn
0
1
Qn
(c)
(a)
J
f
Q
K
Q
(b)
For clock=0
S=R=1 and FF
maintains its
previous state
When J=K=1
then S=Q
and FF toggles
Problem – if JK flip-flop in a toggle state (J=K=1) can flip again
For instance when Q=1, and J=K=1, then only R goes low and
and Q changes to 0. If the clock is still high, the feedback
disables K and enables J and FF changes its output again
EE415 VLSI Design
Other Flip-Flops
T
J
f
f
K
Q
D
J
f
Q
f
Q
Q
K
T
Q
D
Q
f
Q
f
Q
Toggle Flip-Flop
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Delay Flip-Flop
(D-latch)
Race Problem
tloop
t
f
1
D
Q
f
Q
Signal can race around during f = 1
EE415 VLSI Design
t
Master-Slave Flip-Flop
SLAVE
MASTER
J
S
Q
K
R
Q
SI
RI
S
Q
Q
R
Q
Q
f
PRESET
EE415 VLSI Design
J
f
Q
K
Q
CLEAR
Master transmits the signal
to the output during the
high clock phase and
slave is waiting for the
clock to change this
prevents race conditions
Propagation Delay Based Edge-Trigger
f
Circuit which produces
a short output impulse
used in edge triggered devices
N1
In
f
X
In
N2
X
tp LH
Out
Out
= Mono-Stable Multi-Vibrator
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Edge Triggered Flip-Flop
J
S
Q
Q
R
Q
Q
f
K
J
No need for master-slave
configuration
EE415 VLSI Design
Q
f
K
Q