EDK Overview
© 2004 Xilinx, Inc. All Rights Reserved
Objectives
After completing this module, you will be able to:
•
•
•
•
•
•
Describe the embedded systems development flow
Understand the components in the hardware design
Specify ways to create a hardware design
Identify the tools included in the EDK
Locate the EDK documentation
List the supported operating systems
EDK Overview - 1 - 3
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
•
•
Introduction
EDK
–
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–
•
•
•
EDK Overview - 1 - 4
Project Management
Software Application
Management
Platform Management
Hardware Design
PlatGen
Supported Platforms
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Embedded Systems
•
An embedded system is nearly any computing system (other than a
general-purpose computer) with the following characteristics
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Single-functioned
•
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Tightly constrained
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•
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EDK Overview - 1 - 5
Tuned for low cost
Single-to-fewer components based
Performs functions fast enough
Consumes minimum power
Reactive and real-time
•
–
Typically, is designed to perform predefined function
Must continually monitor the desired environment and react to changes
Hardware and software co-existence
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Embedded Systems
•
Examples:
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Mobile phone systems
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Automotive applications
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Flight-control systems, engine controllers, auto-pilots and passenger in-flight
entertainment systems
Defense systems
•
EDK Overview - 1 - 6
Braking systems, traction control, airbag release systems, and cruise-control
applications
Aerospace applications
•
–
Customer handsets and base stations
Radar systems, fighter aircraft flight-control systems, radio systems, and
missile guidance systems
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Current Technologies
•
•
•
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Microcontroller-based systems
DSP processor-based systems
ASIC technology
FPGA technology
EDK Overview - 1 - 7
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Integration in System Design
Integration of Functions
Embedded Software Tools
CPU
CPU
Embedded Software Tools
Embedded Software Tools
FPGA
I/O
FPGA +
Memory + IP +
High Speed IO
(4K & Virtex)
Logic Design Tools
Memory
Logic + Memory
+ IP +
Processors +
RocketIO
(Virtex-II Pro)
Logic Design Tools
Programmable Systems
usher in a new era of system
design integration
possibilities
Logic Design Tools
Time
EDK Overview - 1 - 8
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Embedded Design
in an FPGA
•
Embedded design in an FPGA consists of the following:
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FPGA hardware design
C drivers for hardware
Software design
•
EDK Overview - 1 - 9
RTOS versus Main + ISR
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
PowerPC-based Embedded Design
RocketIO
DSOCM
BRAM
Dedicated Hard IP
PowerPC
405 Core
Off-Chip
Memory
EDK Overview - 1 - 10
OPB
Processor Local Bus
Hi-Speed
Peripheral
e.g.
Memory
Controller
ZBT SSRAM
DCR Bus
Data
PLB
Flexible Soft IP
GB
E-Net
DDR SDRAM
IBM CoreConnect™
on-chip bus standard
PLB, OPB, and DCR
Bus
On-Chip Peripheral Bus
Bridge
UART
SDRAM
© 2004 Xilinx, Inc. All Rights Reserved
GPIO
Arbiter
Arbiter
Instruction
ISOCM
BRAM
On-Chip
Peripheral
Full system customization to meet
performance, functionality, and
cost goals
For Academic Use Only
MicroBlaze-based Embedded Design
Local Memory
MicroBlaze
Bus
32-Bit RISC Core
LocalLink™
FIFO Channels
0,1…….32
Custom
Functions
Arbiter
D-Cache
BRAM
Instruction
Bus
Processor Local Bus
Bridge
Hi-Speed
Peripheral
10/100
E-Net
Data
PLB
On-Chip Peripheral Bus
UART
EDK Overview - 1 - 11
Configurable
Sizes
Possible in Dedicated Hard IP
PowerPC
Virtex-II Pro
405 Core
OPB
Custom
Functions
Off-Chip
Memory
Flexible Soft IP
e.g.
Memory
Controller
GB
E-Net
On-Chip
Peripheral
FLASH/SRAM
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Arbiter
BRAM
I-Cache
BRAM
Outline
•
•
Introduction
EDK
–
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–
•
•
•
EDK Overview - 1 - 12
Project Management
Software Application
Management
Platform Management
Hardware Design
PlatGen
Supported Platforms
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Embedded Development
Tool Flow Overview
Standard Embedded SW
Development Flow
Standard FPGA HW
Development Flow
C Code
VHDL/Verilog
Compiler/Linker
Synthesizer
(Simulator)
Simulator
Object Code
Place & Route
Data2MEM
?
CPU code in
off-chip
memory
CPU code in
on-chip
memory
?
Bitstream
Download to FPGA
Download to Board & FPGA
Debugger
EDK Overview - 1 - 13
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
EDK
•
The Embedded Development Kit (EDK) consists of the following:
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Xilinx Platform Studio – XPS
Base System Builder – BSB
Creating/Importing IP Wizard
Hardware generation tool – PlatGen
Library generation tool – LibGen
Simulation generation tool – SimGen
GNU software development tools
System verification tool – XMD
Processor IP
Drivers for IP
Documentation
Use the GUI or the shell command tool to run the EDK tool
EDK Overview - 1 - 14
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
EDK
MHS File
system.mhs
Processor IP
MPD Files
PlatGen
system.ucf
Source Code
Source Code
Synthesis
Compile
MSS File
system.mss
EDIF
IP Netlists
Object Files
LibGen
ISE/Xflow
Link
Libraries
system.bit
Data2MEM
Executable
download.bit
Hardware
EDK Overview - 1 - 15
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Xilinx Platform Studio
System
Details
View
System
Diagram
View
Source
Code
Editor
Integrated Hardware and Software
System Development Tools
EDK Overview - 1 - 16
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
XPS Functions
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Project management
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MHS or MSS file
XMP file
Platform management
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Software application
management
–
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Tool flow settings
Software platform settings
Tool invocation
Debug and simulation
HW/SW
Simulation
Hardware
Design
XPS
HW/SW
Debug
Software
Design
EDK Overview - 1 - 17
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
•
•
Introduction
EDK
–
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•
•
•
EDK Overview - 1 - 18
Project Management
Software Application
Management
Platform Management
Hardware Design
PlatGen
Supported Platforms
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Project Management
•
Create a new project
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Using Base System Builder
Using Platform Studio
New Project toolbar button
•
•
Open an existing project
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Opens a Platform Studio GUI
Import existing MHS file
Select the Target Device
Specify a single Peripheral Repository
Project information is saved in the Xilinx Microprocessor Project
(XMP) file
EDK Overview - 1 - 19
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Create a Project Using Base
System Builder (BSB)
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•
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Select a target board
Select a processor
Configure the processor
Select and configure
I/O interfaces
Add internal peripherals
Generate the system software
and the linker script
Generate the design
–
system.mhs
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data/system.ucf
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etc/fast_runtime.opt
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etc/download.cmd
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system.bsb (optional, if selected)
–
TestApp/src/TestApp.c (optional, if selected)
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TestApp/src/TestAppLinkScr (optional, if selected)
EDK Overview - 1 - 20
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Project Creation Using BSB
1
Identify Location and
Project File Name
2
Select a Board Vendor,
Name, and Revision
2AAlternatively, you can start
with an already built
project and make changes
EDK Overview - 1 - 21
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Project Creation Using BSB
3
EDK Overview - 1 - 22
4
Select a processor
© 2004 Xilinx, Inc. All Rights Reserved
Configure the processor and
bus speeds, and debug
For Academic Use Only
Project Creation Using BSB
5
Select and configure I/O
6
5A
EDK Overview - 1 - 23
Add internal peripherals
Number of peripherals
displayed will depend on the
screen size and resolution
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Project Creation Using BSB
7
Configure software
application and linker script
Deselecting this option
will not generate software
application and linker script
7C
EDK Overview - 1 - 24
© 2004 Xilinx, Inc. All Rights Reserved
7A
Assign stdin and stout
devices if present
7B
Assign memory blocks
for various purposes
For Academic Use Only
Project Creation Using BSB
8
EDK Overview - 1 - 25
Generate the system
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Project Creation
Through Platform Studio
or
1
2
EDK Overview - 1 - 26
© 2004 Xilinx, Inc. All Rights Reserved
Identify Location and
Project File Name
Identify Target Device
For Academic Use Only
Project Creation
Through Platform Studio
4
3
EDK Overview - 1 - 27
Select and Edit the Address
Map for Each Module
Select modules from the
catalog and click Add to
instantiate them in your
design
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Project Creation
Through Platform Studio
Add buses to the project
5
6
EDK Overview - 1 - 28
Identify the bus to which
modules are attached as Slave
or Master
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
•
•
Introduction
EDK
–
–
–
•
•
•
EDK Overview - 1 - 29
Project Management
Software Application
Management
Platform Management
Hardware Design
PlatGen
Supported Platforms
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Software Application
Management
•
•
•
•
•
•
XPS supports test application creation and linker script management
through BSB
XPS allows users to specify multiple application projects in the
Applications tab
XPS has an integrated editor for viewing and editing the C source and
header files of the user program
The source code is grouped for each processor instance. You can add
or delete the list of source code files for each processor
All of the source code files for a processor are compiled by using the
compiler specified for that processor
XPS tracks changes to C/C++ source files and recompiles when
necessary
EDK Overview - 1 - 30
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
•
•
Introduction
EDK
–
–
–
•
•
•
EDK Overview - 1 - 31
Project Management
Software Application
Management
Platform Management
Hardware Design
PlatGen
Supported Platforms
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Process Management
•
Platform management tasks of XPS include
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Librarie and device driver configuration (LibGen)
Simulation model generation (SimGen)
Implementation (Xflow or ISE)
Compilation (GNU Compiler)
Bitstream initialization (Data2MEM)
To change the system specification and software settings, XPS supports
the following features and processes
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–
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–
EDK Overview - 1 - 32
Add/Edit Cores (Dialog)
Software Platform Settings
Tool Flow Settings
Tool Invocation
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Add/Edit Cores (Dialog)
•
Design and modify the hardware system
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Add peripherals
•
•
•
•
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Delete peripherals
•
•
•
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Processor
Bus-specific IP
Custom IP
Change (add/delete/modify) settings
•
•
•
EDK Overview - 1 - 33
Processor: PowerPC or MicroBlaze
Bus: PLB, OPB, OCM
Add bus-specific IP
Customize IP
Base address and end address
Parameters
Ports
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Software Platform Settings
•
•
Used to set all the software platform related options in the design
Has multiple tabs
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Software Platform
•
•
•
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Processor and Drivers Parameters
•
•
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Compilers
Core clock frequency
Library/OS Parameters
•
•
EDK Overview - 1 - 34
Drivers
Libraries
Kernel and Operating Systems
Stdin and stdout devices
Malloc function usage option
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Project Options Settings
•
XPS supports project options settings for
–
–
–
EDK Overview - 1 - 35
Device and Repository
Hierarchy and Flow
Simulation
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Project Options
Device and Repository Tab
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Set/Change Target Device
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Peripheral Repository Directory
–
•
Architecture
Device Size
Package
Grade
Provide path to custom IP
not present in the current
project directory structure
Custom Makefile Directory
Note: Detailed information on the other
two tabs is provided in the Adding
Your Own IP to the OPB Bus module and the System Simulation module
EDK Overview - 1 - 36
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
•
•
Introduction
EDK
–
–
–
•
•
•
EDK Overview - 1 - 37
Project Management
Software Application
Management
Platform Management
Hardware Design
PlatGen
Supported Platforms
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Hardware Design Example
•
We will build the following system from scratch
(while no components are present in the system)
OPB
Bus
PLB
Bus
PPC
UART
INTC
PLB2OPB
PLB BRAM
Cntlr
PLB BRAM
Cntlr
PLB BRAM
Timer
GPIO
PLB BRAM
GPIO
•
We will start with
Project  Add/Edit Cores … (Dialog)
EDK Overview - 1 - 38
© 2004 Xilinx, Inc. All Rights Reserved
MY IP
GPIO
For Academic Use Only
Add/Edit Cores
Peripherals Tab
•
•
In XPS, select
Project  Add/Edit
Cores... to open
the System Settings
dialog
Select one or more
cores to be included
into the system MHS
file, then click << Add
EDK Overview - 1 - 39
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Embedded Design Progress
OPB
Bus
PLB
Bus
PPC
UART
INTC
PLB2OPB
PLB BRAM
Cntlr
PLB BRAM
Cntlr
Timer
PLB BRAM
GPIO
PLB BRAM
GPIO
MY IP
GPIO
Having placed the processor and peripherals, add buses
EDK Overview - 1 - 40
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Add/Edit Cores
Bus Connections Tab
Select and add the
buses required in the
system
2• Specify the bus
to which each peripheral
is connected as master
or slave
3• Specify the BRAMs
to the correct
Memory Controllers
1•
EDK Overview - 1 - 41
1
2
3
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Hardware Design Progress
OPB
Bus
PLB
Bus
PPC
UART
INTC
PLB2OPB
PLB BRAM
Cntlr
PLB BRAM
Cntlr
Timer
PLB BRAM
GPIO
PLB BRAM
GPIO
MY IP
GPIO
Having assigned bus connections, connect internal and external ports
EDK Overview - 1 - 42
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Add/Edit Cores
Ports Tab
1• Filter ports by
2•
3•
4•
5•
instance or string
Add/Remove
ports to be
connected
Connect
component ports
using nets and
Specify net names
Specify if a net is
internal or external
Specify net sizes
EDK Overview - 1 - 43
1
3
4
5
2
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Defining a Connection
1 Select ports to be
connected (use Shift
or Ctrl keys)
1
2 Click Connect
3
Enter the net name used
for the connection
4 Specify whether a net is
2
3
4
internal or external
EDK Overview - 1 - 44
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Hardware Design Progress
PowerPC
Processor System Reset
RSTC405RESETCHIP
RSTC405RESETCORE
RSTC405RESETSYS
C405RSTCHIPRESETREQ
C405RSTCORERESETREQ
C405RSTSYSRESETREQ
RSTC405RESETCHIP
RSTC405RESETCORE
RSTC405RESETSYS
CHIP_RESET_REQ
CORE_RESET_REQ
SYSTEM_RESET_REQ
JTAG PPC
JTGC405TCK
JTGC405TDI
JTGC405TMS
JTGC405TDO
JTGC405TDOEN
JTGC405TCK
JTGC405TDI
JTGC405TMS
JTGC405TDO
JTGC405TDOEN
Once ports are connected, each device can be configured
for specific functionalities
EDK Overview - 1 - 45
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Add/Edit Cores
Parameters Tab
1
Define the IP Peripheral
parameters for each
core
3
2
Default values are
shown
2
Overriding
values
1
3
Overriding values
can be entered
EDK Overview - 1 - 46
Default values
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
•
•
Introduction
EDK
–
–
–
•
•
•
EDK Overview - 1 - 47
Project Management
Software Application
Management
Platform Management
Hardware Design
PlatGen
Supported Platforms
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
EDK
MHS File
system.mhs
Processor IP
MPD Files
PlatGen
Source Code
Source Code
Synthesis
Compile
MSS File
system.mss
EDIF
IP Netlists
Object Files
LibGen
ISE/Xflow
Link
Libraries
Focus Here
system.ucf
system.bit
Data2MEM
Executable
download.bit
Hardware
EDK Overview - 1 - 48
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Hardware Design
•
Platform Generator (PlatGen) inputs the following files:
–
–
•
•
MHS file
MPD file
PlatGen constructs the embedded processor system in the form of
hardware netlists (HDL and implementation netlist files)
MHS file parameters override the MPD parameters
–
EDK Overview - 1 - 49
The MPD parameters are the defaults
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Hardware Design
Microprocessor Hardware
Specification File
Microprocessor Peripheral
Definitions File
MHS overrides MPD
MPD contains all of the defaults
EDK Overview - 1 - 50
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
PlatGen
PlatGen Generated Directories
•
HDL directory
–
project_directory
–
hdl directory
–
implementation directory
•
Implementation directory
–
synthesis directory
–
–
•
peripheral_wrapper.ngc files
system.ngc file
system.bmm file
Synthesis directory
–
–
EDK Overview - 1 - 51
system.[vhd|v] file (if top-level)
system_stub.[vhd|v] file (if sub-module)
peripheral_wrapper.[vhd|v] files
peripheral_wrapper.[prj|scr] files
system.[prj|scr] files
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
PlatGen Memory Generation
•
Memory generation
–
–
Platform Generator generates the necessary banks of memory and the
initialization files for the BRAM block (bram_block). The BRAM block is
coupled with a BRAM controller
Current BRAM controllers include the following:
•
•
•
•
•
EDK Overview - 1 - 52
DSOCM BRAM Controller (dsbram_if_cntlr)
ISOCM BRAM Controller (isbram_if_cntlr)
PLB BRAM Controller (plb_bram_if_cntlr)
OPB BRAM Controller (opb_bram_if_cntlr)
LMB BRAM Controller (lmb_bram_if_cntlr)
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
PlatGen Memory Sizes
•
Memory sizes
OPB, LMB, OCM Buses
•
PLB Bus
Memory must be built on 2n boundaries
–
–
EDK Overview - 1 - 53
Let n be the number of address pins on the memory, and let I be the unsigned
number formed by the starting address or memory size. If I is the integer, then the
memory is built on the 2n boundary
One-KB memory at $4000 is at the 2n boundary; whereas, one KB at $4100 is not
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
BlockMemory Map
•
•
A BMM (BlockRAM Memory Map) file contains a syntactic description of
how individual BlockRAMs constitute a contiguous logical data space
PlatGen has the following policy for writing a BMM file:
–
–
–
EDK Overview - 1 - 54
If PORTA is connected and PORTB is not connected, then the BMM
generated will be from PORTA point of reference
If PORTA is not connected and PORTB is connected, then the BMM
generated will be from PORTB point of reference
If PORTA is connected and PORTB is connected, then the BMM generated
will be from PORTA point of reference
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
•
•
Introduction
EDK
–
–
–
•
•
•
EDK Overview - 1 - 55
Project Management
Software Application
Management
Platform Management
Hardware Design
PlatGen
Supported Platforms
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Supported Platforms
•
Operating systems
–
–
–
–
•
Windows 2000 (Service Pack 2)
Windows XP
Solaris 2.8/2.9
Linux Red Hat
FPGA families
–
–
–
–
–
–
EDK Overview - 1 - 56
Spartan-II (MicroBlaze)
Spartan-IIE (MicroBlaze)
Spartan III (MicroBlaze)
Virtex  and Virtex E (MicroBlaze)
Virtex-II (MicroBlaze)
Virtex-II Pro (MicroBlaze and PowerPC)
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
BSB Supported Platforms
•
Some of the Hardware boards
–
–
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–
–
–
•
Avnet Virtex-II Pro Development Board
Avnet Spartan -III Evaluation Board
Memec design Spartan -IIE Development Boards
Memec design Virtex-II MicroBlaze Development Board
Memec design Virtex-II Pro Development Boards
Xilinx Spartan -III Starter Board
Xilinx ML300 board
Xilinx ML310 board
Others available from the Board Vendor
EDK Overview - 1 - 57
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Review Questions
•
•
•
What is the smallest memory size that PlatGen can generate for a
Spartan-IIE device?
Why is the address 0xFFFF_B100, NOT a valid BASEADDR for a LMB
BRAM controller?
What will the BAUDRATE for the peripheral be:
–
–
EDK Overview - 1 - 59
If the MPD has the following parameter: C_BAUDRATE = 9600
If the MHS has the following parameter: C_BAUDRATE = 115200
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Answers
•
What is the smallest memory size that PlatGen can generate for a
Spartan-IIE device?
–
•
Why is the address 0xFFFF_B100, NOT a valid BASEADDR for a LMB
BRAM Controller?
–
•
2 KB
It is not on a 2n boundary
What will the BAUDRATE for the peripheral be:
–
–
EDK Overview - 1 - 60
If the MPD has the following parameter: C_BAUDRATE = 9600
If the MHS has the following parameter: C_BAUDRATE = 115200
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Memory Space
•
How do you build a 48-KB OPB BRAM memory space for a
MicroBlaze processor in a Virtex-II device?
0x0000_0000
? KB
0x
? KB
EDK Overview - 1 - 61
© 2004 Xilinx, Inc. All Rights Reserved
0x
0x
For Academic Use Only
Memory Space
•
How do you build a 48-KB OPB BRAM memory space for a
MicroBlaze processor in a Virtex-II device?
0x0000_0000
32 KB
0x0000_7FFF
16 KB
EDK Overview - 1 - 62
© 2004 Xilinx, Inc. All Rights Reserved
0x0000_8000
0x0000_BFFF
For Academic Use Only
Memory Requirement
•
How many block RAMs do you think will be used to build a 16-KB PLB
memory space for a PowerPC processor in a Virtex-II Pro device?
And why?
EDK Overview - 1 - 63
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Memory Requirement
•
How many block RAMs do you think will be used to build a 16-KB PLB
memory space for a PowerPC processor in a Virtex-II Pro device?
And why?
–
–
EDK Overview - 1 - 64
Eight block RAMs will be used
Because PowerPC allows a byte write, the memory is organized in a bytewide mode. The Virtex-II Pro block RAM has 18 Kb; each block will be
configured in 2K x 8. This will require eight block RAMs
© 2004 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Where Can I Learn More?
•
Tool documentation
–
–
–
–
•
Processor documentation
–
–
–
•
Getting Started with the Embedded Development Kit
Processor IP Reference Guide
Embedded Systems Tools Guide
Xilinx Drivers
PowerPC Processor Reference Guide
PowerPC 405 Processor Block Reference Guide
MicroBlaze Processor Reference Guide
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