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Department of Electrical and Computer Engineering
University of Colorado at Colorado Springs
"Engineering for the Future"
Dr. Ciletti, ciletti@vlsic.uccs.edu
rev 02-22-2003
The objective of this tutorial is to enable students to get a "jump start" using the Xilinx Integrated
Software Environment (ISE) FPGA synthesis tool set. This tutorial is a work in progress – please report any errors and/or suggestions for improvement to Dr. Ciletti.
Additional Xilinx documentation can be downloaded from www.xilinx.com. Online documentation is located at http://www.support.xilinx.com
. Also see the the Xilinx University Resource Center located at http://xup.msu.edu
.
1. GETTING STARTED
Invoke the Xilinx ISE tool with the shortcut icon shown in Fig 1.
Figure 1.
Xilinx ISE: Desktop icon.
This action will activate Project navigator and display the window shown in Fig. 2.

Figure 2.
Xilinx ISE: Project Navigator.
2.
XILINX ISE DESIGN PROJECT
The files associated with a design are grouped and referred to as a "project." A project must be created before any work can be done. At the menu bar click on File , and select a New Project , then OK . These actions will open the New Project dialog box, shown in Fig. 3.
Figure 3.
Xilinx ISE: "New Project" window.
The window shows the Project name and the default Project Location .
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1.
Insert a name for the project, e.g. ALU_mach . The name will be applied to certain files generated by the system.
2.
Insert a location (folder) that will house the project. It is recommended that you locate the project within your file structure on the network. Do not leave files on the lab machines.
3.
Click on the Value window for the Synthesis Tool property name and select XST Verilog (the default is shown as XST VHDL ).
4.
Insert/select a device, e.g. xc2s200-5pq208.
5.
Click OK .
The Verilog files for a design can be associated with a declared project. To add source files to the project, click on Project at the Project Navigator menu bar, and select Add source from the drop-down menu.
Browse to the location of the source file (a test file with a .v extesion) and select the file. Project
Navigoator will compile the file and check for syntax errors.
1 The Project Navigator window will now display a hierarchy of the files in the projct and indicate their status (e.g., successfully compiled), as shown in Fig. 4. Every error must tbe corrected. The built-in editor can be used to edit the source code.
1 Note: the syntax check will flag as an error a usage of the language that is not supported by the synthesis tool., e.g., a model that includes a user-defined primitive or a iniitial behavior.

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Figure 4.
Project Navigator: A hierarchy of source files is displayed after they are added to the project.
3. ISE DESIGN FLOW
A window below the hierarchy browser window displays the four process steps in the ISE desgin flow:
Design Entry Utilities , Synthesize , Implement Design , and Create Programming File . An entry in the list must execute successfully before a lower entry can execute.
4. Pin Assignment

To choose your PIN Assignments:
* In process window, go to Design Entry Utilities * User Constraints *
Edit Implementation Constraints (Constraints Editor)
* This will open a new Constraints Editor window.
* Click on the Ports Tab
* Type the desired pin number (include the prefix p for each pin, e.g., p74) for each input/output port in the "Location" field
* Then just exit out of the window
* If you have synthesize before performing this step, when you exit out of the Constraints Editor window, you will see a message which asks if you would like to retain the old pin settings or reset them to the new settings you entered. If you choose to reset the settings, the pin numbers you entered will be saved, and the project will re-synthesize
To Implement and Download Design:
* If you had not synthesized previous to completing your pin assignments, double click on Synthesize in the Processes Window.
* When synthesis is completed - a green check will appear beside this process
* Then, in the Processes window, double click "Implement Design"
* When implementation is complete, a green check will appear beside the implement process.
* In the process window, go to Implement Design * Place & Route * Pad
Report
* Double click on "Pad Report" and check the pad report to make sure the pin numbers you entered for each port were assigned to the correct place
* If all pin assignments are correct, in the processes window, under
"Generate Programming Files," double click on Generate PROM file. This will create a .bin file, and open a PROM editing window. We can close this window as soon as we see the .bin file was created, since we are not using a
PROM device.
* Under "Generate Programming Files", double click on "Configure
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Device".
* This will bring up a new window with a picture of a Xilinx chip displayed...click on the chip to highlight it, then go to the "Operations" drop down window, and select "Program"
* You must have the board already connected to the serial port before selecting Configure Device command.
Note: Every program will need a specification for the JTAG clock. The Startup options tab is the location for access to the JTAG clock. See Figure 5.
Figure 5.